Abstract: An apparatus for recognizing a failure in a cryptographic unit, wherein the cryptographic unit includes a determinator for determining an input control signal and an output control signal, with the determinator being formed to determine the input control signal on the basis of an encryption of an input control signal parity of a group of input signals or an input signal of the group of input signals with an encryption number and to determine the output control signal on the basis of an encryption of an output control signal parity of a group of the output signals or an output signal of the group of output signals with the encryption number. Furthermore, the apparatus for recognizing includes an evaluator for evaluating the input control signal and the output control signal to recognize a failure of the cryptographic unit on the basis of a comparison between the input control signal and the output control signal.

Abstract: An integrated circuit having a first circuit unit, which is put into a power-saving mode by a control apparatus and into a predetermined initial state when changing from the power-saving mode to a regular operating state. A second circuit unit is put into a power-saving mode by the control apparatus, during which the second circuit unit buffer-stores data and/or instructions adopted immediately prior to the power-saving state, with the second circuit unit resuming and providing the data and/or instructions when changing from the power-saving mode to the regular operating state. The second circuit unit has an input connection to which a first potential is applied in order to change to the power-saving mode and during the power-saving mode, and to which a second potential is applied in order to change to the operating state and during the operating state.

Abstract: A data storage medium having a memory unit, a control unit, and an interface having contact pads for at least one voltage supply and one data transmission. Provision is made of a test signal generating device for generating test signals used to test the data storage medium. The data storage medium can be switched into a test mode in which the test signals are used for the test.

Abstract: A parallel data bus having a plurality of bus lines, and a bus mode switching device for switching between data transmission at a high data transmission rate and data transmission at high data integrity.

Abstract: Method and system for operating a cache memory. The method includes the steps of splitting the cache memory into sets, addressing the cache memory using a processor address which is split into at least two fields, and forming one of the fields of the processor address for addressing the cache memory from a combinational logic function on a basis of a modulo N operation, where N corresponds to the number of sets in the cache memory.

Abstract: A bit sequence which is generated by a feedback shift register is decimated with a variable decimation value m (m?|N) in a predetermined manner which is known on the decryption side, i.e. in that every mth bit of the bit sequence is picked out from the bit sequence so as to obtain the key bit stream.

Abstract: A random number generator includes a plurality of memory cells arranged in a series, a feedback processor for generating a feedback signal and for feeding the feedback signal into one of the memory cells, and a random number outputter formed to combine states of a group of at least two memory cells to obtain an output sequence. Sequences strongly differing from one another, the number of which is greater than the number of memory cells, can be generated by generating several output sequences AF0, AF1, AF2, . . . , AFk by combining states of different memory cells such that a safe and efficient bus encryption is achievable.

Abstract: A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump command. The processor has a command processor, which is adapted in the mother program upon occurrence of the sub-program jump command, to extract back-up information about data required in the mother program after processing the sub-program from the sub-program jump command, to back-up data required in the mother program after execution of the sub-program based on the back-up information, to extract a destination address from the sub-program jump command, which refers to the sub-program, and to effect the continuation of the processing of the program with the sub-program based on the destination address.

Abstract: Device for generating random numbers having a pseudo random number generator, a memory and a sequential controller. The pseudo random number generator generates a deterministic random number sequence after an initialization using an initialization value. The memory stores initialization information, wherein the initialization information is derived from a true random number or corresponds to the true random number. The sequential controller initializes the pseudo random number generator at start-up using the initialization information or the information derived from the initialization information, stores an intermediate state of the pseudo random number generator or information derived from the intermediate state in the memory at a turn-off of the pseudo random number generator, and uses the intermediate state or the information derived from the intermediate state for an initialization of the pseudo random number generator at a renewed start-up.

Abstract: A pseudorandom number generator includes a unit for providing a number of 2n sequences of numbers, n being greater than or equal to 2. The sequences of numbers are combined by a unit such that at first all the sequences of numbers are combined with one another in an intermediate processing stage to obtain an intermediate processing sequence, and that subsequently a subgroup of k sequences of numbers is combined with the intermediate processing sequence in a final processing stage to obtain the output sequence.

Abstract: A data storage device includes a plurality of data storage units, a physical random number generator with a noise source based on a physical noise process, for generating a random number, and a replacer for selecting a data storage unit wherein data is to be stored, depending on the random number. Selecting, on the basis of genuine random numbers, data storage units and/or lines to be replaced in the cache.

Abstract: A pseudorandom number generator includes a first elemental shift register having a non-linear feedback feature, a second elemental shift register and combiner for combining signals at an output of the first elemental shift register and the second elemental shift register to obtain a combined signal representing a pseudorandom number. The combination of individual non-linear elemental shift registers allows a safe and flexible implementation of random number generators, the output sequences of which include a high linear complexity and a high period length.

Abstract: Key management device for electronic memories and a method for the encrypted storage of digital data words in electronic memories, in which each stored data word is encrypted with a digital keyword, which may be different from another digital keyword of another stored data word.

Abstract: A shift device for shifting a first place of a data word, which consists of a plurality of places, to a second place so as to obtain a shifted data word, wherein the first place is encrypted using a first encryption parameter and wherein the second place is encrypted using a second encryption parameter, includes a unit for shifting the first place of the data word to the second place of the data word, a unit for re-encrypting the first place from an encryption using the first encryption parameter into an encryption using the second encryption pa- rameter, and a control for controlling the unit for shifting and the unit for re-encryption so that the first place is first shifted to the second place and is then re-encrypted, or that the first place is first re-encrypted and is then shifted to the second place. This ensures that data encrypted either with the first encryption parameter or with the second encryption parameter are always shifted, thus making it harder for attackers to eavesdrop on clear text data.

Abstract: A calculating unit for performing an arithmetic operation with at least two operands, the at least two operands being encrypted, includes an arithmetic-logic unit with a first input for the first encrypted operand, a second input for the second encrypted operand, a third input for an encryption parameter and an output for an encrypted result of the operation, the arithmetic-logic unit being formed so as to operate on the first input, the second input and the third input by means of arithmetic sub-operations, while considering the type of encryption of the operands, such that at the output, an encrypted result is obtained which equals a value that would be obtained if the first operand was subjected to the arithmetic operation in a non-encrypted state and if the second operand would be subjected to the arithmetic operation in a non-encrypted state, and a result obtained was subsequently encrypted, no decryption of the operands being performed in the arithmetic-logic unit.

Abstract: A method for determining a physical address from a virtual address, wherein a mapping regulation between the virtual address and the physical address is implemented as hierarchical tree structure with compressed nodes. First, a compression indicator included in the mapping regulation is read, and a portion of the virtual address associated with the considered node level is read. Using the compression indicator and the portion of the virtual address, an entry in the node list of the considered node is determined. The determined entry is read, whereupon the physical address can be determined directly, if the considered node level has been the hierarchically lowest node level. If higher node levels to be processed are present, the previous steps in determining the physical address for compressed nodes of lower hierarchy level are repeated until the hierarchically lowest node level is reached.

Abstract: Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a synchronization value to determine which memory entries of the data area are to be synchronized with the main memory. A cache logic circuit of the cache memory then compares the synchronization value with contents of a memory field of each memory entry. When there is a match, the cache logic circuit checks a flag of a third memory field of the identification area for a first state, which indicates that a change was made to the data area of the memory entry since the last synchronization. When the flag is in the first state, the contents of the data area are transferred to the main memory.

Abstract: A cache memory serves for accelerating accesses to an external memory of a microprocessor. Instead of an actually occurring hit event, a cache miss is signaled to the microprocessor. The reversal is randomly controlled. This disguises the current profile of cache hit and miss events, which enhances the security against statistical attack techniques based on the evaluation of the current profile.

Abstract: In a cache memory whose addresses are split into tag, index and offset parts, a transformation device is provided in hardware form for performing a transformation between a respective tag part of the address and a coded tag address that is unambiguous in both directions. In addition, the index field of the addresses of the cache memory can be encoded by another mapping procedure that maps the index field onto a coded index field and is unambiguous in both directions. A hardware unit of suitable configuration is also used for this purpose.

Abstract: A circuit configuration for detecting an unwanted attack on an integrated circuit has a signal line to which a clock signal is applied and at least one line pair which is respectively used to code a bit. The signal line and the at least one line pair are connected between a first and a second circuit block in the integrated circuit. The signal line and the at least one line pair are connected to a detector circuit which changes the operating sequence in the integrated circuit on the basis of the signals on the signal line and on the at least one line pair. The detector circuit can be used to the same extent to test for production faults.