Abstract: An apparatus for recognizing a failure in a cryptographic unit, wherein the cryptographic unit includes a determinator for determining an input control signal and an output control signal, with the determinator being formed to determine the input control signal on the basis of an encryption of an input control signal parity of a group of input signals or an input signal of the group of input signals with an encryption number and to determine the output control signal on the basis of an encryption of an output control signal parity of a group of the output signals or an output signal of the group of output signals with the encryption number. Furthermore, the apparatus for recognizing includes an evaluator for evaluating the input control signal and the output control signal to recognize a failure of the cryptographic unit on the basis of a comparison between the input control signal and the output control signal.

Abstract: A key-generating apparatus is provided for generating a session key which is known to a first communication apparatus and a second communication apparatus, for the first communication apparatus, from secret information which may be determined by the first and second communication apparatuses. The key-generating apparatus includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information, and a second module operable to use the session key for communication with the second communication apparatus.

Abstract: A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier.

Abstract: A system and method for controlling a device. Data that was encrypted using a first encryption scheme is decrypted, then re-encrypted using a second encryption scheme. The re-encrypted data is then decrypted.

Abstract: A device for generating a session key which is known to a first communication partner and a second communication partner, for the first communication partner, from secret information which may be determined by the first and second communication partners, includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information. The device also includes a second module operable to use the session key for communication with the second communication partner.

Abstract: A compiler module for providing instruction signature support to a compiler includes a language construct identifier and a placeholder insertion component. The language construct identifier is configured to identify an instruction signature-relevant language construct in a high level language source code supplied to the compiler. The placeholder insertion component is configured to interact with the compiler for inserting at least one instruction signature-related placeholder based on the instruction signature-related language construct into a compiled code processed by the compiler on the basis of the high level language source code.

Abstract: A device according to the present invention is configured for transmitting data between two semiconductor chips of a data processor in an encrypted manner, wherein a first semiconductor chip is connected to a second semiconductor chip. The device includes a non-volatile memory element in each of the two semiconductor chips, wherein an encryption initial value for an encryption rule is stored in the memory element of the first semiconductor chip and a decryption initial value associated to the encryption initial value for a decryption rule associated to the encryption rule is stored in the memory element of the second semiconductor chip. Additionally, the first semiconductor chip has a first data transmission interface formed to generate an encryption data stream from an input data stream using the encryption initial value according to the encryption rule.

Abstract: A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.

Abstract: A random bit stream generator includes an internal state memory for storing a current internal state of the random bit stream generator and a periodic bit sequence generator configured to provide a periodic bit sequence. An output function receives a bit sequence portion of the periodic bit sequence and a first internal state portion of the current internal state. A new output bit of the random bit stream is determined, by the output function, based on a Boolean combination of the bit sequence portion and the first internal state portion. A feedback arrangement feeds the new output bit back to the internal state memory by performing a Boolean combination involving the new output bit and a second internal state portion of the current internal state to determine a next internal state of the random bit generator.

Abstract: A data-processing apparatus has a data provider for providing an input datum encrypted by an encryption key. In addition, the data-processing apparatus has a key stream generator for generating a key stream in a predetermined deterministic manner such that the key stream has a decryption key corresponding to the encryption key. Furthermore, the data-processing apparatus has a data processor for processing the encrypted input datum in a masked manner using the decryption key as a temporary key to obtain an output datum encrypted by an output key such that the encrypted output datum corresponds to a result, encrypted by the output key, of a predetermined operation on the encrypted input datum having been decrypted by the decryption key.

Abstract: A system and method for controlling a device. Data that was encrypted using a first encryption scheme is decrypted, then re-encrypted using a second encryption scheme. The re-encrypted data is then decrypted.

Abstract: An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload symbol and a previous coding symbol or an initialization symbol to obtain a combined symbol, and map the combined symbol using a mapping rule to obtain a current coding symbol. The mapping rule is based on a power of two or more of a companion matrix of a characteristic polynomial of a linear feedback shift register. The apparatus is configured such that the checksum corresponds to the current coding symbol, when the number of payload symbols is processed by the coder, the number being one or greater than one.

Abstract: A method for processing an operating sequence of instructions of a program in a processor, wherein each instruction is represented by an assigned instruction code which comprises one execution step to be processed by the processor or a plurality of execution steps to be processed successively by the processor, includes determining an actual signature value assigned to a current execution step of the execution steps of the instruction code representing the instruction of the operating sequence; determining, in a manner dependent on an address value, a desired signature value assigned to the current execution step; and if the actual signature value does not correspond to the desired signature value, omitting at least one execution step directly available for execution and/or an execution step indirectly available for execution.

Abstract: A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic.

Abstract: A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF At and performing a preliminary correction of the potentially erroneous PUF At by means of a stored correction vector Deltat-1, to obtain a preliminarily corrected PUF Bt. The PUF A is reconstructed from the preliminarily corrected PUF Bt by means of an error correction algorithm. A corresponding apparatus is also provided.

Abstract: An encryption device encrypts a first block of user data to obtain a first encryption result and encrypts a second block of user data, which follows the first block of user data, to obtain a second encryption result. The encryption device uses the first encryption result for encrypting the second block of user data. An extractor extracts a first portion of the first encryption result, the first portion being smaller than the first encryption result, and a second portion of the second encryption result, the second portion being smaller than the second encryption result. A message formatter combines the first block of user data and the first portion as a signature for the first block to produce a first transmission packet, and combines the second block of user data and the second portion as a signature for the second block to produce a second transmission packet.

Abstract: A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier.

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.

Abstract: A compiler module for providing instruction signature support to a compiler includes a language construct identifier and a placeholder insertion component. The language construct identifier is configured to identify an instruction signature-relevant language construct in a high level language source code supplied to the compiler. The placeholder insertion component is configured to interact with the compiler for inserting at least one instruction signature-related placeholder based on the instruction signature-related language construct into a compiled code processed by the compiler on the basis of the high level language source code.

Abstract: An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload symbol and a previous coding symbol or an initialization symbol to obtain a combined symbol, and map the combined symbol using a mapping rule to obtain a current coding symbol. The mapping rule is based on a power of two or more of a companion matrix of a characteristic polynomial of a linear feedback shift register. The apparatus is configured such that the checksum corresponds to the current coding symbol, when the number of payload symbols is processed by the coder, the number being one or greater than one.