Abstract: Embodiments described herein provide an apparatus, computer readable digital storage medium and method for producing an instruction sequence for a computation unit which can be controlled by a program which includes at least the instruction sequence.

Abstract: A signature module calculates a signature during the execution of a program by a central processing unit based on program instructions to the central processing unit, and stores the signature in a signature register of the signature module. The signature module includes: a calculation unit configured to generate a signature value based on program instructions executed on the central processing unit; and an instruction information interface configured to receive at least one item of instruction information from the central processing unit which indicates whether an instruction currently being executed by the central processing unit was jumped to indirectly or directly.

Abstract: By arranging a redundancy means and a control means upstream from an encryption means which encrypts and decrypts the data to be stored in an external memory, the integrity of data may be ensured when the generation of redundancy information is realized by the redundancy means, and when the generation of a syndrome bit vector indicating any alteration of the data is implemented by the control means. What is preferred is a control matrix constructed from idempotent, thinly populated, circulant square sub-matrices only. By arranging redundancy and control means upstream from the encryption/decryption means, what is achieved is that both errors in the encrypted data and errors of the non-encrypted data may be proven, provided that they have occurred in the data path between the redundancy/control means and the encryption/decryption means.

Abstract: A device and method for a secure execution of a program. The program includes a sequence of program commands including use and checking commands. A checking value is generated according to a setup regulation when executing a checking command. A control value is generated according to the setup regulation and the checking value is compared to the control value. An insecure execution of the program is indicated when the checking value and the control value do not match.

Abstract: One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

Abstract: An encryption device encrypts a first block of user data to obtain a first encryption result and encrypts a second block of user data, which follows the first block of user data, to obtain a second encryption result. The encryption device uses the first encryption result for encrypting the second block of user data. An extractor extracts a first portion of the first encryption result, the first portion being smaller than the first encryption result, and a second portion of the second encryption result, the second portion being smaller than the second encryption result. A message formatter combines the first block of user data and the first portion as a signature for the first block to produce a first transmission packet, and combines the second block of user data and the second portion as a signature for the second block to produce a second transmission packet.

Abstract: One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

Abstract: A communication device for transmitting data to a communication partner device includes a transmitter for transmitting transmit data to the communication partner device, a determiner for determining a check value from the transmit data in accordance with a determination specification, a receiver for receiving a verification value from the communication partner device, and a checker configured to compare the check value with the verification value and to provide a fault indication signal as a function of the comparison.

Abstract: A data storage device includes a plurality of data storage units, a physical random number generator with a noise source based on a physical noise process, for generating a random number, and a replacer for selecting a data storage unit wherein data is to be stored, depending on the random number. Selecting, on the basis of genuine random numbers, data storage units and/or lines to be replaced in the cache.

Abstract: A system and method for transferring information include generating a public/private key pair for programming equipment and sending the programming equipment public key to a certificate authority. A programming equipment certificate is generated using the programming equipment public key and a private key of the certificate authority. The programming equipment certificate and a certificate authority certificate are sent to the programming equipment. Information is transferred to or from the programming equipment in response to an authentication using the programming equipment certificate and the certificate authority certificate.

Abstract: An integrated circuit has one or more logic gates and a control circuit. The control circuit has one or more control elements coupled to the logic gates. The control circuit controls the states of the one or more logic gates. The one or more control elements have one or more programmable resistance elements and/or one or more threshold switching elements.

Abstract: A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit.

Abstract: A random number generator includes a plurality of memory cells arranged in a series, a feedback processor for generating a feedback signal and for feeding the feedback signal into one of the memory cells, and a random number outputter formed to combine states of a group of at least two memory cells to obtain an output sequence. Sequences strongly differing from one another, the number of which is greater than the number of memory cells, can be generated by generating several output sequences AF0, AF1, AF2, . . . , AFk by combining states of different memory cells such that a safe and efficient bus encryption is achievable.

Abstract: One or more embodiments relate to an electronic device comprising a circuitry and a programmable resistive element. The programmable resistive element comprises a first and a second state, wherein the programmable resistive element is configured to allow switching from the second state into the first state in response to a signal comprising at least a predefined level. The circuitry is configured to provide signals up the predefined level, wherein the circuitry is configured to provide a switch signal to the programmable resistive element, wherein the switch signal causes switching from the first into the second state.

Abstract: A device for generating a session key which is known to a first communication partner and a second communication partner, for the first communication partner, from secret information which may be determined by the first and second communication partners, includes a first module operable to calculate the session key using a concatenation of at least a part of a random number and a part of the secret information. The device also includes a second module operable to use the session key for communication with the second communication partner.

Abstract: A semiconductor chip having a subcircuit formed in a substrate; and a phase-change memory cell located on the subcircuit, and configured to directly detect an attack on the subcircuit, or to form a shield to prevent physical access to the subcircuit.

Abstract: A communication apparatus for communication according to a master-slave communication protocol is formed as a slave instance communicating with a master instance via a bus. The master instance is operative to switch the bus into a bus suspend state if no bus activity is present during a predetermined interval. In response to a bus suspend state, the slave instance makes a transition to a slave suspend state. The communication apparatus includes a monitor configured to monitor the bus activity and a transmitter configured to transmit a signal via the bus if the monitor does not recognize any bus activity during part of the predetermined interval and a transition of the slave instance to the slave suspend state is undesirable, wherein the signal is operative to prevent the master instance from switching the bus into the bus suspend state.

Abstract: A bit sequence which is generated by a feedback shift register is decimated with a variable decimation value m (m?|N) in a predetermined manner which is known on the decryption side, i.e. in that every mth bit of the bit sequence is picked out from the bit sequence so as to obtain the key bit stream.

Abstract: A security circuit comprising including a sensor located remotely from a central alarm handler and configured to sense an attack, and a phase-change memory cell coupled to and located remotely with the sensor, and configured to store an alarm event when the attack is sensed.

Abstract: In a device for determining a position of a bit error in a bit sequence, a check matrix is used which has a predefined number of rows and a predefined number of columns. The check matrix includes a plurality of square submatrices having a submatrix row number and a submatrix column number corresponding to the predefined number of rows or the predefined number of columns of the check matrix. The device for determining then includes a unit for receiving a bit sequence and a unit for identifying a syndrome using the check matrix and the received bit sequence.