Patents by Inventor Bernhard Goller

Bernhard Goller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12652995
    Abstract: A method of manufacturing a semiconductor device in a semiconductor body is proposed. The method includes processing a semiconductor body at a first surface of the semiconductor body. The method further includes attaching the semiconductor body to a carrier via the first surface. The carrier includes an inner part and an outer part at least partly surrounding the inner part. The method further includes processing the semiconductor body at a second surface opposite to the first surface. The method further includes detaching the inner part of the carrier from the semiconductor body.
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: June 9, 2026
    Assignee: Infineon Technologies AG
    Inventors: Gregor Langer, Bernhard Goller, Nilesha Mishra, Matteo Piccin, Franz-Josef Pichler
  • Patent number: 12412740
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: September 9, 2025
    Assignee: Infineon Technologies AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20250253168
    Abstract: An apparatus for electrochemical treating of a semiconductor substrate comprising at least one first tank filled with an electrolyte and comprising at least one first electrode, at least one second tank filled with an electrolyte and comprising at least one second electrode, and a separation unit that electrically separates the first and second tanks including their electrolytes, an electric power supply connected to the first and second electrodes, a transport means, which is configured for transporting the substrate over the first and second tanks, and a controller for controlling the transport means in a specific manner. Further, a process for electrochemical treating of a semiconductor substrate using the apparatus described herein is disclosed.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 7, 2025
    Inventors: Iris Moder, Bernhard Goller, Petra Erika Fischer, Norbert Bay, Xavier Gay
  • Publication number: 20250183031
    Abstract: A method of processing a semiconductor wafer includes: forming one or more epitaxial layers over a first main surface of the semiconductor wafer; forming one or more porous layers in the semiconductor wafer or in the one or more epitaxial layers, wherein the semiconductor wafer, the one or more epitaxial layers and the one or more porous layers collectively form a substrate; forming doped regions of a semiconductor device in the one or more epitaxial layers; and after forming the doped regions of the semiconductor device, separating a non-porous part of the semiconductor wafer from a remainder of the substrate along the one or more porous layers.
    Type: Application
    Filed: February 5, 2025
    Publication date: June 5, 2025
    Inventors: Bernhard Goller, Alexander Binter, Tobias Hoechbauer, Martin Huber, Iris Moder, Matteo Piccin, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 12249504
    Abstract: pa The method of processing a semiconductor wafer includes forming one or more epitaxial layers over its first main surface. It also involves forming one or more porous layers within the semiconductor wafer or within the epitaxial layers. Together, the semiconductor wafer, the epitaxial layer(s), and the porous layer(s) form a substrate. Next, doped regions of a semiconductor device are formed within the epitaxial layer(s). After forming these doped regions, a non-porous part of the semiconductor wafer is separated from the rest of the substrate along the porous layer(s).
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: March 11, 2025
    Assignee: Infineon Technologies AG
    Inventors: Bernhard Goller, Alexander Christian Binter, Tobias Hoechbauer, Martin Huber, Iris Moder, Matteo Piccin, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 12211703
    Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.
    Type: Grant
    Filed: August 22, 2023
    Date of Patent: January 28, 2025
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
  • Patent number: 12060266
    Abstract: A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: August 13, 2024
    Assignee: Infineon Technologies AG
    Inventors: Andre Brockmeier, Markus Bergmeister, Bernhard Goller, Daniel Pieber, Sokratis Sgouridis
  • Publication number: 20240153759
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 9, 2024
    Inventors: Iris MODER, Bernhard GOLLER, Tobias Franz Wolfgang HOECHBAUER, Roland RUPP, Francisco Javier SANTOS RODRIGUEZ, Hans-Joachim SCHULZE
  • Publication number: 20240030032
    Abstract: The present disclosure generally relates to a method of manufacturing a contact on a silicon carbide semiconductor substrate wherein the method comprises providing a 4H—SiC semiconductor substrate, irradiating a surface area of the 4H—SiC semiconductor substrate with a first thermal annealing laser beam, thereby generating a phase separation of the surface area comprising at least a 3C—SiC layer, and depositing a contact material onto the 3C—SiC layer to form a contact layer on the semiconductor substrate. The disclosure further relates to a silicon carbide semiconductor device with an Ohmic contact comprising a 4H—SiC semiconductor substrate, a 3C—SiC layer, and a contact layer directly in contact with the 3C—SiC layer at the semiconductor surface.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 25, 2024
    Inventors: Saurabh ROY, Ravi Keshav JOSHI, Hans-Joachim SCHULZE, Bernhard GOLLER, Daria KRASNOZHON
  • Patent number: 11881397
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: January 23, 2024
    Assignee: Infineon Technologies AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20240006218
    Abstract: A method of manufacturing a semiconductor device in a semiconductor body is proposed. The method includes processing a semiconductor body at a first surface of the semiconductor body. The method further includes attaching the semiconductor body to a carrier via the first surface. The carrier includes an inner part and an outer part at least partly surrounding the inner part. The method further includes processing the semiconductor body at a second surface opposite to the first surface. The method further includes detaching the inner part of the carrier from the semiconductor body.
    Type: Application
    Filed: June 20, 2023
    Publication date: January 4, 2024
    Inventors: Gregor Langer, Bernhard Goller, Nilesha Mishra, Matteo Piccin, Franz-Josef Pichler
  • Publication number: 20230395394
    Abstract: A method of forming a semiconductor device includes: forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate; increasing the porosity of the first semiconductor layer; first annealing the first semiconductor layer in an atmosphere including an inert gas; forming a second semiconductor layer on the first semiconductor layer; and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer. Additional methods of forming a semiconductor device are described.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
  • Patent number: 11810779
    Abstract: A method includes: in a semiconductor wafer having a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a front surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10?2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer, wherein forming the porous region comprises bringing in contact a porosifying agent with the front surface of the first semiconductor layer and applying a voltage between the first semiconductor layer and a first electrode that is in contact with the porosifying agent, wherein applying the voltage comprises applying the voltage between the first electrode and an edge region of the first semiconductor layer.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: November 7, 2023
    Assignee: Infineon Technologies AG
    Inventors: Sophia Friedler, Bernhard Goller, Iris Moder, Ingo Muri
  • Publication number: 20230330769
    Abstract: Provided is a machining apparatus including a profile sensor unit configured to obtain shape information about a parent substrate; and a laser scan unit configured to direct a laser beam onto the parent substrate, wherein a laser beam axis of the laser beam is tilted to an exposed main surface of the parent substrate, and wherein a track of the laser beam on the parent substrate is controllable as a function of the shape information obtained from the profile sensor unit.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko David Swoboda
  • Patent number: 11742215
    Abstract: A method of forming a semiconductor device, including forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer being of the same dopant type as the semiconductor substrate, the first semiconductor layer having a higher dopant concentration than the semiconductor substrate, increasing the porosity of the first semiconductor layer, first annealing the first semiconductor layer at a temperature of at least 1050° C., forming a second semiconductor layer on the first semiconductor layer and separating the second semiconductor layer from the semiconductor substrate by splitting within the first semiconductor layer.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: August 29, 2023
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Alexander Breymesser, Bernhard Goller, Matthias Kuenle, Helmut Oefner, Francisco Javier Santos Rodriguez, Stephan Voss
  • Patent number: 11712749
    Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: August 1, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko Swoboda
  • Publication number: 20230238442
    Abstract: A semiconductor device includes a semiconductor substrate and a metal nitride layer above the semiconductor substrate. The metal nitride layer forms at least one interface region with the semiconductor substrate. The at least one interface region includes a first portion of the semiconductor substrate, a first portion of the metal nitride layer, and an interface between the first portion of the semiconductor substrate and the first portion of the metal nitride layer. A concentration of nitrogen content at the first portion of the metal nitride layer is higher than a concentration of nitrogen content at a second portion, of the metal nitride layer, outside the interface region. A distribution of nitrogen content throughout the metal nitride layer may have a maximum concentration at the first portion of the metal nitride layer. Alternatively and/or additionally, a method for producing such a semiconductor device is provided herein.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 27, 2023
    Inventors: Ravi Keshav JOSHI, Romain ESTEVE, Saurabh ROY, Bernhard GOLLER, Werner SCHUSTEREDER, Kristijan Luka MLETSCHNIG
  • Publication number: 20230127556
    Abstract: A method of processing a semiconductor wafer includes: forming one or more epitaxial layers over a first main surface of the semiconductor wafer; forming one or more porous layers in the semiconductor wafer or in the one or more epitaxial layers, wherein the semiconductor wafer, the one or more epitaxial layers and the one or more porous layers collectively form a substrate; forming doped regions of a semiconductor device in the one or more epitaxial layers; and after forming the doped regions of the semiconductor device, separating a non-porous part of the semiconductor wafer from a remainder of the substrate along the one or more porous layers.
    Type: Application
    Filed: May 12, 2022
    Publication date: April 27, 2023
    Inventors: Bernhard Goller, Alexander Binter, Tobias Hoechbauer, Martin Huber, Iris Moder, Matteo Piccin, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Publication number: 20220359194
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Application
    Filed: July 20, 2022
    Publication date: November 10, 2022
    Inventors: Iris MODER, Bernhard GOLLER, Tobias Franz Wolfgang HOECHBAUER, Roland RUPP, Francisco Javier SANTOS RODRIGUEZ, Hans-Joachim SCHULZE
  • Patent number: 11476111
    Abstract: A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 18, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Iris Moder, Bernhard Goller, Tobias Franz Wolfgang Hoechbauer, Roland Rupp, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze