Abstract: A semiconductor device includes a doped Si base substrate, one or more device epitaxial layers formed over a main surface of the doped Si base substrate, a diffusion barrier structure, and a gate formed above the diffusion barrier structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si formed in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers.

Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.

Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate adjacent the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, a diffusion barrier structure formed along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si, and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.

Abstract: According to various embodiments, a support table may include: a baseplate including a support structure, the support structure defining a support region over the baseplate to support at least one of a workpiece or a workpiece carrier therein; and one or more light-emitting components disposed between the baseplate and the support region. The one or more light-emitting components are configured to emit light into the support region.

Abstract: A panel according to an embodiment includes a translucent layer arrangement and a battery cell embedded at least partially into the translucent layer arrangement.

Abstract: A method for processing a silicon carbide wafer includes implanting ions into the silicon carbide wafer to form an absorption layer in the silicon carbide wafer. The absorption coefficient of the absorption layer is at least 100 times the absorption coefficient of silicon carbide material of the silicon carbide wafer outside the absorption layer, for light of a target wavelength. The silicon carbide wafer is split along the absorption layer at least by irradiating the silicon carbide wafer with light of the target wavelength to obtain a silicon carbide device wafer and a remaining silicon carbide wafer.

Abstract: A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.

Abstract: An implantable vessel fluid sensor is configured to sense at least one vessel fluid parameter of a vessel. The implantable vessel fluid sensor includes a tubular body having a first end portion. The first end portion is configured to be inserted into and to form a sealed junction with an open vessel end of the vessel. The implantable vessel fluid sensor further includes a sensor unit connected to the tubular body. The sensor unit includes a sensor region configured to be in direct contact with the vessel fluid in a sealed junction state. A minimum distance between the sensor region and the first end portion is at most 10 times an outer diameter of the first end portion of the tubular body.

Abstract: A method for manufacturing a semiconductor device includes: partially dicing a substrate wafer arrangement having a plurality of semiconductor chips, wherein the partial dicing forms trenches around the semiconductor chips on a front-side of the substrate wafer arrangement, the depth being greater than a target thickness of a semiconductor chip; filling the trenches with a polymer material to form a polymer structure; first thinning of the back-side to expose portions of the polymer structure; forming a conductive layer on the back-side of the substrate wafer arrangement so that the exposed portions of the polymer structure are covered; second thinning of the back-side to form insular islands of conductive material, the insular islands separated from each other by the polymer structure, each insular island corresponding to a respective one of the semiconductor chips; and dicing the substrate wafer arrangement along the polymer structure.

Abstract: A method of manufacturing a semiconductor device includes forming an auxiliary mask including a plurality of mask openings on a main surface of a crystalline semiconductor substrate. A porous structure is formed in the semiconductor substrate. The porous structure includes a porous layer at a distance to the main surface and porous columns that extend from the porous layer into direction of the main surface and that are laterally separated from each other by a non-porous portion. A non-porous device layer is formed on the non-porous portion and on the porous columns.

Abstract: According to various embodiments, a workpiece planarization arrangement may include: a chuck including at least one portion configured to support one or more workpieces; and a planarization tool configured to planarize the at least one portion of the chuck and to planarize one or more workpieces on the at least one portion of the chuck; wherein the at least one portion of the chuck includes at least one of particles, pores and/or a polymer.

Abstract: A battery electrode in accordance with various embodiments may include: a substrate including a surface configured to face an ion-carrying electrolyte; and a first diffusivity changing region at a first portion of the surface, wherein the first diffusivity changing region is configured to change diffusion of ions carried by the electrolyte into the substrate, and wherein a second portion of the surface is free from the first diffusivity changing region.

Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.

Abstract: A method of manufacturing a lithium ion battery includes: attaching a lid to a first main surface of a first substrate, the lid including a conductive coves element; forming a cavity between the lid and the first substrate; forming an anode comprising a component made of a semiconductor material at the first substrate; forming a cathode at the lid; and filling an electrolyte into the cavity.

Abstract: A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.

Abstract: A lithium ion battery includes a first substrate having a first main surface, and a lid including an insulating material. The lid is attached to the first main surface of the first substrate, and a cavity is defined between the first substrate and the lid. The lithium ion battery further includes an electrical interconnection element in the lid, the electrical interconnection element providing an electrical connection between a first main surface and a second main surface of the lid. The lithium ion battery further includes an electrolyte in the cavity, an anode at the first substrate, the anode including a component made of a semiconductor material, and a cathode at the lid.

Abstract: A semiconductor device includes a semiconductor substrate having an upper first main face and first and second recess areas formed in the upper first main face, a battery arranged at the first recess area and one or more of a shock sensor and an acceleration sensor arranged at the second recess area. The shock sensor or the acceleration sensor includes a movable mass, a cantilever connected to the moveable mass, a piezoelectric layer applied to the cantilever, and a wiring connected to the piezoelectric layer. The wiring has first and second terminals. The moveable mass and part of the cantilever are arranged above the second recess area, so that the shock sensor or the acceleration sensor delivers a voltage between the first and second terminals, a strength of the voltage being dependent on a strength of a shock or acceleration exerted on the semiconductor device.

Abstract: According to various embodiments, a workpiece planarization arrangement may include: a chuck including a support carrier; and a workpiece-support replaceably mounted on the support carrier; and a planarization tool configured to planarize the at least one portion of the workpiece-support and to planarize one or more workpieces on the at least one portion of the workpiece-support.

Abstract: According to various embodiments, a workpiece planarization arrangement may include: a chuck including a support carrier; and a workpiece-support replaceably mounted on the support carrier; and a planarization tool configured to planarize the at least one portion of the workpiece-support and to planarize one or more workpieces on the at least one portion of the workpiece-support.

Abstract: According to various embodiments, a workpiece planarization arrangement may include: a chuck including at least one portion configured to support one or more workpieces; and a planarization tool configured to planarize the at least one portion of the chuck and to planarize one or more workpieces on the at least one portion of the chuck; wherein the at least one portion of the chuck includes at least one of particles, pores and/or a polymer.