Patents by Inventor Bernhard Sell

Bernhard Sell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240234579
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Application
    Filed: February 16, 2024
    Publication date: July 11, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Publication number: 20240222509
    Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
    Type: Application
    Filed: March 18, 2024
    Publication date: July 4, 2024
    Inventor: Bernhard SELL
  • Patent number: 12015087
    Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: June 18, 2024
    Assignee: Intel Corporation
    Inventor: Bernhard Sell
  • Patent number: 11991873
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
  • Patent number: 11973105
    Abstract: An integrated circuit structure comprises at least one metal gate formed in a first dielectric layer, the at least one metal gate comprising a workfunction layer and the gate oxide layer along sidewalls of the first dielectric layer. A field effect (FE) dielectric layer dielectric layer is above the first dielectric layer of the at least one metal gate. A precision resistor comprising a thin-film metallic material is formed on the FE dielectric layer above the at least one metal gate and extending laterally over the at least one metal gate.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Leif Paulson, Kinyip Phoa, Shi Liu
  • Patent number: 11955560
    Abstract: A thin film transistor (TFT) structure includes a gate electrode, a gate dielectric layer on the gate electrode, a channel layer including a semiconductor material with a first polarity on the gate dielectric layer. The TFT structure also includes a multi-layer material stack on the channel layer, opposite the gate dielectric layer, an interlayer dielectric (ILD) material over the multi-layer material stack and beyond a sidewall of the channel layer. The TFT structure further includes source and drain contacts through the interlayer dielectric material, and in contact with the channel layer, where the multi-layer material stack includes a barrier layer including oxygen and a metal in contact with the channel layer, where the barrier layer has a second polarity. A sealant layer is in contact with the barrier layer, where the sealant layer and the ILD have a different composition.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Arnab Sen Gupta, Travis W. LaJoie, Sarah Atanasov, Chieh-Jen Ku, Bernhard Sell, Noriyuki Sato, Van Le, Matthew Metz, Hui Jae Yoo, Pei-Hua Wang
  • Patent number: 11950407
    Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Juan G. Alzate Vinasco, Travis W. Lajoie, Abhishek A. Sharma, Kimberly L Pierce, Elliot N. Tan, Yu-Jin Chen, Van H. Le, Pei-Hua Wang, Bernhard Sell
  • Patent number: 11929415
    Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Travis W. Lajoie
  • Patent number: 11908911
    Abstract: A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang
  • Publication number: 20240049450
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 8, 2024
    Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Jared STOEGER, Yu-Wen HUANG, Shu ZHOU
  • Patent number: 11832438
    Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Jared Stoeger, Yu-Wen Huang, Shu Zhou
  • Publication number: 20230369501
    Abstract: Techniques are provided herein for forming transistor devices with reduced parasitic capacitance, such as transistors used in a memory structure. In an example, a given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT), and the storage device may include a capacitor. Any of the given TFTs may include a dielectric liner extending along sidewalls of the TFT. The TFT includes a recess (e.g., a dimple) that extends laterally inwards toward a midpoint of a semiconductor region of the TFT. The dielectric liner thus also pinches or otherwise extends inward. This pinched-in dielectric liner may reduce parasitic capacitance between the contacts of the TFT and the gate electrode of the TFT. The pinched-in dielectric liner may also protect the contacts from forming too deep into the semiconductor region.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Cheng Tan, Yu-Wen Huang, Hui-Min Chuang, Xiaojun Weng, Nikhil J. Mehta, Allen B. Gardiner, Shu Zhou, Timothy Jen, Abhishek Anil Sharma, Van H. Le, Travis W. Lajoie, Bernhard Sell
  • Patent number: 11810980
    Abstract: Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Pei-Hua Wang, Bernhard Sell, Martin M. Mitan, Leonard C. Pipes
  • Publication number: 20230326860
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Application
    Filed: June 6, 2023
    Publication date: October 12, 2023
    Inventors: Bernhard SELL, Oleg GOLONZKA
  • Patent number: 11784088
    Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang, Harish Ganapathy, Leonard C. Pipes
  • Patent number: 11784257
    Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventor: Bernhard Sell
  • Publication number: 20230317720
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Inventors: Guannan LIU, Akm A. AHSAN, Mark ARMSTRONG, Bernhard SELL
  • Patent number: 11758711
    Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Yih Wang, Abhishek A. Sharma, Tahir Ghani, Allen B. Gardiner, Travis W. Lajoie, Pei-Hua Wang, Chieh-Jen Ku, Bernhard Sell, Juan G. Alzate-Vinasco, Blake C. Lin
  • Patent number: 11728335
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: August 15, 2023
    Assignee: Intel Corporation
    Inventors: Guannan Liu, Akm A. Ahsan, Mark Armstrong, Bernhard Sell
  • Patent number: 11721630
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Bernhard Sell, Oleg Golonzka