Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

Abstract: Described herein are integrated circuit devices with lined interconnects. Interconnect liners can help maintain conductivity between semiconductor devices (e.g., transistors) and the interconnects that conduct current to and from the semiconductor devices. In some embodiments, metal interconnects are lined with a tungsten liner. Tungsten liners may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Abstract: Disclosed herein are IC structures with three-dimensional capacitors with double metal electrodes provided in a support structure (e.g., a substrate, a die, a wafer, or a chip). An example three-dimensional capacitor includes first and second capacitor electrodes and a capacitor insulator between them. Each capacitor electrode includes a planar portion extending across the support structure and one or more via portions extending into one or more via openings in the support structure. The capacitor insulator also includes a planar portion and a via portion extending into the via opening(s). The planar portion of the capacitor electrodes are thicker than the via portions. Each capacitor electrode may be deposited using two deposition processes, such as a conformal deposition process for depositing the via portion of the electrode, and a sputter process for depositing the planar portion of the electrode.

Abstract: A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

Abstract: A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

Abstract: Transistors with metal oxide channel material that is in-situ doped for desired charge carrier concentrations. The metal oxide channel material may be deposited by atomic layering of multiple constituent metals with an oxidation of each layer. Such an ALD process may be performed by cyclically depositing a precursor of one of the metals upon a substrate during a deposition phase, and oxidizing the absorbed precursor during an oxidation phase. For a quinary metal oxide, each of three metal precursors may be introduced and oxidized during the ALD process, and charge carrier concentrations may be modulated by further introducing a fourth metal precursor during the ALD process in a manner that disperses this dopant metal within the film at a significantly lower chemical concentration than the other metals.

Abstract: Transistors with metal oxide channel material and a multi-composition gate dielectric. A surface of a metal oxide gate dielectric may be nitrided before deposition of a metal oxide channel material, for example to reduce gate capacitance of a TFT. Breakdown voltage and/or drive current of a TFT can be increased through the introduction of an additional metal oxide and/or nitride between the gate electrode and a metal oxide gate dielectric. The introduction of an intervening layer between two layers of a metal oxide gate dielectric can also increase breakdown voltage and/or drive current of a TFT.

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

Abstract: This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate.

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.