Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. The semiconductor device further includes a capacitor having a bottom plate above the substrate, a capacitor dielectric layer adjacent to and above the bottom plate, and a top plate adjacent to and above the capacitor dielectric layer. The bottom plate, the capacitor dielectric layer, and the top plate are within the first ILD layer or the second ILD layer. Furthermore, an air gap is formed next to the top plate and below a top surface of the second ILD layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a transistor above a substrate. The transistor includes a channel layer above the substrate. The channel layer includes a first channel material of a first conductivity. In addition, the channel layer further includes elements of one or more additional materials distributed within the channel layer. The channel layer including the elements of the one or more additional materials has a second conductivity different from the first conductivity. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract: A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.

Abstract: Thin film transistors having alloying source or drain metals are described. In an example, an integrated circuit structure includes a semiconducting oxide material over a gate electrode. A pair of conductive contacts is on a first region of the semiconducting oxide material. A second region of the semiconducting oxide material is between the pair of conductive contacts. The pair of conductive contacts includes a metal species. The metal species is in the first region of the semiconducting oxide material but not in the second region of the semiconducting oxide material.

Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

Abstract: Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

Abstract: This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.