Abstract: A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array.

Abstract: A device has a flexible substrate supporting an array of magnetic sensors exposed to a uniform external magnetic field. One or more controllers receive magnetic sensor signals from the magnetic sensors. The one or more controllers collect reference magnetic sensor signals when the flexible substrate is aligned with the uniform external magnetic field. The one or more controllers collect first polarity magnetic sensor signals in response to deformation of the flexible substrate in a first direction. The one or more controllers collect second polarity magnetic sensor signals in response to deformation of the flexible substrate in a second direction. The magnetic sensor signals establish a profile of the orientation of the flexible substrate with respect to the uniform external magnetic field.

Abstract: A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array. Input patterns can be loaded into a DRAM array by loading logic state ones (“1”) into each of the plurality of input data bit lines in each of the columns in the DRAM array and shunting one or more of the plurality of input data bit lines in the DRAM array corresponding to logic state zeroes (“0”) in the input pattern.

Abstract: An apparatus includes groups of magnetic tunnel junctions, where the magnetic tunnel junctions in each group are arranged in rows, the magnetic tunnel junctions in each row are connected in series, and the rows are connected in parallel. The apparatus further includes a first conductive layer including conductive interconnects, a second conductive layer including straps, and a third conductive layer including field lines, each field line configured to generate a magnetic field for configuring an operating point of a corresponding subset of the magnetic tunnel junctions in each group based on a current flow through each field line. The magnetic tunnel junctions in each group are disposed between and connected to a corresponding one of the conductive interconnects and a corresponding one of the straps. The second conductive layer is disposed between the first conductive layer and the third conductive layer.

Abstract: An apparatus includes circuits including a first circuit and a second circuit, each circuit including subarrays of magnetic tunnel junctions, where: (1) the magnetic tunnel junctions in each subarray are arranged in rows, the magnetic tunnel junctions in each row are connected in series, and the rows are connected in parallel; and (2) the subarrays are connected in series. The apparatus further comprises a field line configured to generate a first magnetic field for configuring an operating point of the first circuit based on a current flow through the field line, where the impedance of a subset of the plurality of rows in each subarray of magnetic tunnel junctions included in the first circuit is configured based on the first magnetic field.

Abstract: An apparatus includes circuits and a module configured to determine an external magnetic field based on a parameter of each circuit. Each circuit includes an array of magnetic tunnel junctions partitioned into subarrays. The magnetic tunnel junctions in each subarray are arranged in rows, the magnetic tunnel junctions in each row are connected in series, and the rows are connected in parallel. The subarrays are connected in series. Each magnetic tunnel junction includes a storage layer having a storage magnetization and a sense layer having a sense magnetization. Each magnetic tunnel junction is configured such that the sense magnetization and impedance of each magnetic tunnel junction vary in response to an external magnetic field. The parameter of each circuit varies based on a combined impedance of the multiple magnetic tunnel junctions. The module is implemented in at least one of a memory or a processing device.

Abstract: An apparatus includes circuits including a first circuit and a second circuit, each circuit including subarrays of magnetic tunnel junctions, where: (1) the magnetic tunnel junctions in each subarray are arranged in rows, the magnetic tunnel junctions in each row are connected in series, and the rows are connected in parallel; and the subarrays are connected in series. The apparatus further comprises a field line configured to generate a first magnetic field for configuring an operating point of the first circuit based on a current flow through the field line, wherein impedance of one or more of the magnetic tunnel junctions in each of the plurality of rows of each subarray of magnetic tunnel junctions included in the first circuit is configured based on the first magnetic field.

Abstract: A memory circuit using resistive random access memory (ReRAM) arrays in a secure element. The ReRAM arrays can be configured as content addressable memories (CAMs) or random access memories (RAMs) on the same die, with the control circuitry for performing comparisons of reference patterns and input patterns located outside of the ReRAM arrays. By having ReRAM arrays configured as CAMs and RAMs on the same die, certain reference patterns can be stored in CAMs and others in RAMs depending on security needs. For additional security, a heater can be used to erase reference patterns in the ReRAM arrays when desired.

Abstract: A memory circuit using resistive random access memory (ReRAM) arrays in a secure element. The ReRAM arrays can be configured as content addressable memories (CAMs) or random access memories (RAMs) on the same die, with the control circuitry for performing comparisons of reference patterns and input patterns located outside of the ReRAM arrays. By having ReRAM arrays configured as CAMs and RAMs on the same die, certain reference patterns can be stored in CAMs and others in RAMs depending on security needs. For additional security, a heater can be used to erase reference patterns in the ReRAM arrays when desired.

Abstract: A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the memory cell and the stored state of the memory cell are configured to be a plurality of states including a zero state, a one state, a no care state, and an input blocking state. When the input state of the memory cell is the blocking state, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is the no care state. When the stored state of the memory cell is the blocking state, the memory cell is configured to be in the blocking mode unless the input state of the memory cell is the no care state.

Abstract: A method and system for multi-factor authentication. The method involves combining a plurality of authentication patterns into a combined secure pattern by inserting one or more spacing states into the one authentication pattern at locations based on the values of the another authentication pattern.

Abstract: A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on a first analog input to the circuit. Each MTJ is electrically connected to a first and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of the MTJs varies based on the magnetic field. The circuit is configured to mix the first analog input and a second analog input to generate an analog output based on the output of the second output terminal.

Abstract: A memory circuit using dynamic random access memory (DRAM) arrays. The DRAM arrays can be configured as CAMs or RAMs on the same die, with the control circuitry for performing comparisons located outside of the DRAM arrays. In addition, DRAM arrays can be configured for secure authentication where, after the first authentication performed with a non-volatile secure element, subsequent authentications can be performed by the DRAM array. Input patterns can be loaded into a DRAM array by loading logic state ones (“1”) into each of the plurality of input data bit lines in each of the columns in the DRAM array and shunting one or more of the plurality of input data bit lines in the DRAM array corresponding to logic state zeroes (“0”) in the input pattern.

Abstract: A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the memory cell and the stored state of the memory cell are configured to be a plurality of states including a zero state, a one state, a no care state, and an input blocking state. When the input state of the memory cell is the blocking state, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is the no care state. When the stored state of the memory cell is the blocking state, the memory cell is configured to be in the blocking mode unless the input state of the memory cell is the no care state.

Abstract: A method and system for multi-factor authentication. The method involves combining a plurality of authentication patterns into a combined secure pattern by inserting one or more spacing states into the one authentication pattern at locations based on the values of the another authentication pattern.

Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

Abstract: A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on an analog input to the circuit. Each MTJ is electrically connected to a first output terminal and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of each of the MTJs varies based on the magnetic field. The circuit is configured to generate an analog output based on the output of at least one of the first and the second output terminal.

Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

Abstract: A device has a flexible substrate supporting an array of magnetic sensors exposed to a uniform external magnetic field. One or more controllers receive magnetic sensor signals from the magnetic sensors. The one or more controllers collect reference magnetic sensor signals when the flexible substrate is aligned with the uniform external magnetic field. The one or more controllers collect first polarity magnetic sensor signals in response to deformation of the flexible substrate in a first direction. The one or more controllers collect second polarity magnetic sensor signals in response to deformation of the flexible substrate in a second direction. The magnetic sensor signals establish a profile of the orientation of the flexible substrate with respect to the uniform external magnetic field.