Abstract: A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines.

Abstract: A check engine includes a plurality of comparators, each including a plurality of flash cells, where each of the plurality of comparators is configured to store at least one reference bit included in a set of reference bits, and includes an input for presenting at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Abstract: The present semiconductor structure includes a substrate having a planar surface, a semiconductor chip attached to the planar surface of the substrate, the chip preferably being of the same thickness as or thinner than the substrate, and a package body attached to the substrate and to the semiconductor chip. The semiconductor chip and substrate are sufficiently rigidly attached so that substantial force applied parallel to the planar surface of the substrate may be transmitted therebetween, reducing temperature-change stress on solder balls which connect the substrate with a PCB. The semiconductor chip with advantage is thinned to reduce the stress on the solder balls.

Abstract: A method of fabricating a MESFET is comprised of providing a semiconductor material having a channel region formed therein, forming a gate on the semiconductor material over the channel region, forming a spacer adjacent a first portion of the gate disposed on the semiconductor material, and forming a hard mask disposed on a second portion of the gate and on a portion of the semiconductor material.

Abstract: An environmental sensor integrated with high current drive device is provided. An environmental sensor is fabricated on a semiconductor substrate using conventional MOS process used for N-well CMOS logic and DMOS power transistors. An N-well is preferably used as a junction etch stop for micromachining of mechanical sensor components. A high voltage P-type region is used to electrically isolate the high current device from the sensor device. By locating the sensor device away from the high current drive device on a common semiconductor substrate, good performance can be achieved from the sensor even while the high current device dissipates a large amount of power.

Abstract: A semiconductor device having a channel region having a first and a second portion. The first and second portions of the channel region are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

Abstract: A method is provided for making a power device (54) and a small signal device (52) on a bonded silicon substrate (41). A first silicon substrate (10) provided. A first surface (17) is etched to form a plurality of cavities (11) with a depth (13). A dielectric layer (14) is created on the first surface (17), wherein the dielectric layer (14) is created with a thickness less than or equal to the depth of the plurality of cavities. The dielectric layer (14) is patterned so that a plurality of islands (22) of dielectric remain in the cavities. A second silicon substrate (42) is provided. The first and the second silicon substrates (10, 42) are bonded together in such a manner that the islands (22) are buried. A predetermined portion of the first silicon substrate (10) is removed, thereby creating a surface that is suitable for semiconductor device fabrication.

Abstract: A method is provided for making a power device (54) and a small signal device (52) on a bonded silicon substrate (41). A first silicon substrate (10) provided. A first surface (17) is etched to form a plurality of cavities (11) with a depth (13). A dielectric layer (14) is created on the first surface (17), wherein the dielectric layer (14) is created with a thickness less than or equal to the depth of the plurality of cavities. The dielectric layer (14) is patterned so that a plurality of islands (22) of dielectric remain in the cavities. A second silicon substrate (42) is provided. The first and the second silicon substrates (10, 42) are bonded together in such a manner that the islands (22) are buried. A predetermined portion of the first silicon substrate (10) is removed, thereby creating a surface that is suitable for semiconductor device fabrication.

Abstract: A silicon wafer and a III-V semiconductor wafer are bonded together through a bonding interlayer which is deposited on the III-V semiconductor wafer. By forming the bonding interlayer on the III-V semiconductor wafer, rather than the silicon wafer, the bonding process is facilitated, creating a sufficiently strong bond to carry out further processing. The III-V semiconductor wafer is thinned to relieve stress after the bonding procedure. The bonded wafers may be subjected to a second bonding procedure to increase the bond strength. The bonded wafers can then be subjected to high temperature processing used in semiconductor device fabrication.

Abstract: A microprocessor having a monolithically integrated environmental sensor is provided. The microprocessor is shielded from an environmental signal by isolation which is specific to the type of sensor used, thereby allowing the sensor to be exposed to the environmental signal. Optionally, high current drive circuitry is integrated with the microprocessor-sensor circuit to provide a monolithic device which allows control of power loads based in part on output from an environmental sensing device.

Abstract: A semiconductor device having a channel region having a first and a second portion. The first and second portions of the channel region are designed so that only a small portion is substantially depleted during operation. Thus, a semiconductor device having a short gate length is fabricated.

Abstract: A non-silicon substrate is bonded to a silicon substrate with a stress-relief layer between the non-silicon substrate and the silicon substrate. The stress-relief layer reduces the stress between the non-silicon substrate and the silicon substrate. The stress is created by the difference in the thermal expansion coefficients of the two materials. The stress-relief layer may be a low melting point metal, a semiconductor layer having its thermal expansion coefficient close to the thermal expansion coefficient of the non-silicon substrate. The silicon substrate and/or the non-silicon substrate may have a silicon dioxide layer formed thereon such that the silicon dioxide layer is adjacent to the stress-relief layer.

Abstract: A dielectric isolated area is formed by bonding a first and a second wafer. A first wafer having a first and a second major surface is provided. A second wafer having a first and a second major surface is then provided. Trenches are formed in the first surface of the second wafer. Subsequently, a dielectric layer which can be planarized is formed on the surface of the second wafer having trenches formed therein. The first and second wafers are then bonded so that the dielectric layer and the first surface of the first wafer are bonded to each other. A portion of the second surface of the second wafer is then removed down to at least the bottom of each trench.

Abstract: Silicon and non-silicon semiconductor devices are fabricated on a single chip by bonding a silicon wafer to a non-silicon semiconductor substate. Portions of the non-silicon semiconductor substrate are selectively etched to expose the silicon wafer. Semiconductor devices may then be formed in the silicon wafer and on the non-silicon semiconductor substrate. Alternatively, selective epitaxial silicon may be grown where the non-silicon semiconductor substrate was removed. In another embodiment, a non-silicon semiconductor substrate having wells formed therein is bonded to a silicon wafer. The non-silicon semiconductor substrate is then polished until openings are provided to the silicon wafer. Further processing is carried out as described above.

Abstract: A bipolar integrated circuit requiring less silicon area is provided by the use of a three layer epitaxy on top of a substrate. The first epitaxial layer is of the same conductivity type as the substrate and adds additional height to the substrate surrounding the buried layer. The buried layer serves as a collector and it is surrounded by an isolation area. The top two epitaxial layers are of a conductivity type opposite to that of the substrate with the upper most epitaxial layer having a higher dopant density than does the middle epitaxial layer. A master mask is used to provide self-alignment between the isolation area, a collector plug which makes contact to the buried layer, and a base region.