Patents by Inventor Bharat Bhushan

Bharat Bhushan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12190175
    Abstract: Disclosed are techniques for function-defined output streams corresponding to combinations of events published to one or more event notification streams in an event-driven architecture with a plurality of event notification streams. An output function is received defining a combination of event notifications with criteria for selecting which event notifications to combine from one or more event notification streams. The one or more event notification streams are parsed, and event notifications are selected to initialize a new event notification stream, where event notifications in this stream correspond to instances of the output function when provided a set of event notifications from the one or more event notification streams as input values. When an event notification is published to the one or more event notification streams meeting the criteria specified in the output function, the new event notification stream publishes an event notification corresponding to an output value from the output function.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: January 7, 2025
    Assignee: International Business Machines Corporation
    Inventors: Bharat Bhushan, Kaweepoj Phacharintanakul, Wolfgang von Drews, Matthew Whitehead
  • Publication number: 20240421030
    Abstract: A semiconductor device is provided. The semiconductor device includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die at a first location above a back side surface of the logic die, a second plurality of stacked memory dies electrically coupled with the logic die at a second location above the back side surface of logic die, a first dielectric material disposed above the back side surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies, and a dummy die disposed above the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to back side surfaces of the first plurality and second plurality of stacked memory dies through a second dielectric layer having dielectric-dielectric fusion bonding.
    Type: Application
    Filed: May 24, 2024
    Publication date: December 19, 2024
    Inventors: Bharat Bhushan, Amy R. Griffin, Kunal R. Parekh, Akshay N. Singh
  • Publication number: 20240379596
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A through via extends entirely through the substrate. The through via includes a protruding portion that extends beyond the back side of the substrate. A layer of silicon carbon nitride is disposed at the back side of the substrate and along sidewalls of the protruding portion of the through via. A layer of oxide is disposed at the back side of the substrate and at least partially surrounding the protruding portion of the through via. A conductive pad is disposed at a coupling surface of the through via and at least partially extending through the layer of oxide. As a result, a reliable and cost-efficient semiconductor device can be assembled.
    Type: Application
    Filed: May 9, 2024
    Publication date: November 14, 2024
    Inventors: Bharat Bhushan, Terrence B. McDaniel, Kunal R. Parekh, Bret K. Street, Akshay N. Singh
  • Publication number: 20240339433
    Abstract: A semiconductor device with a through dielectric via is disclosed. The semiconductor device assembly can include a semiconductor die and multiple stacks of semiconductor dies coupled with the semiconductor die at different lateral locations. Dielectric material can be disposed at the semiconductor die between the multiple stacks of semiconductor dies. The through dielectric via can extend entirely through the dielectric material to the semiconductor die such that the through dielectric via couples with circuitry at the semiconductor die. In this way, the through dielectric via can provide power to the semiconductor die (e.g., exclusive of the multiple stacks of semiconductor dies).
    Type: Application
    Filed: March 20, 2024
    Publication date: October 10, 2024
    Inventors: Bharat Bhushan, Nevil N. Gajera, Akshay N. Singh, Kunal R. Parekh
  • Publication number: 20240332229
    Abstract: A semiconductor device is provided. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. A dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. A dummy pad can be disposed in the second layer of dielectric material above the plurality of lines and spaced from the dual damascene pad. In doing so, a reliable semiconductor device can be implemented.
    Type: Application
    Filed: March 27, 2024
    Publication date: October 3, 2024
    Inventors: Bharat Bhushan, Tzu Ching Hung, Kyle K. Kirby, Julia VanWinkle, Kyle B. Campbell, Bret K. Street
  • Publication number: 20240297149
    Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a top memory die, and a one or more intermediate memory dies between the top memory die and the logic die. Front sides of the one or more intermediate memory dies at which active circuitry is disposed face a front side of the top memory die. Back sides of the one or more intermediate memory dies opposite the front sides face a back side of the logic die. In doing so, a cost-efficient, low-complexity semiconductor device can be assembled.
    Type: Application
    Filed: January 29, 2024
    Publication date: September 5, 2024
    Inventors: Bharat Bhushan, Akshay N. Singh, Kunal R. Parekh
  • Publication number: 20240282731
    Abstract: A semiconductor device assembly, including a semiconductor die having a frontside surface, a first plurality of bond pads at the frontside surface and a first dielectric layer at the frontside surface; and an interface die having a frontside surface and a backside surface, the interface die including a second plurality of bond pads and a second dielectric layer disposed on the backside surface of the interface die, a third dielectric layer disposed on the frontside surface of the interface die, wherein the third dielectric layer includes a mechanically altered surface opposite the frontside surface of the interface die, and a redistribution layer disposed on the third dielectric layer and above the frontside surface of the interface die, wherein hybrid bonds are disposed between the frontside surface of the semiconductor die and the backside surface of the interface die.
    Type: Application
    Filed: January 5, 2024
    Publication date: August 22, 2024
    Inventors: Bharat Bhushan, Wei Zhou, Debjit Datta, Chaiyanan Kulchaisit, Kyle K. Kirby, Akshay N. Singh
  • Patent number: 12066901
    Abstract: A determination is made that a backup of a database in an availability group provided by a relational database management system (RDBMS) should be performed. The availability group includes a node functioning as a primary node and hosting a primary replica of the database and one or more other nodes functioning as secondary nodes and hosting secondary replicas of the database. The availability group is a clusterless availability group in which the one or more other nodes functioning as secondary nodes are not available as automatic failover targets should the primary node become unavailable. A command is issued to a node in the availability group to obtain a globally unique identifier (GUID) of the availability group. The node is instructed to index a backup of the database against the GUID of the availability group.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: August 20, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Bharat Bhushan, Niketan Kalaskar
  • Publication number: 20240145425
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20240088100
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 14, 2024
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11876068
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: January 16, 2024
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20240014170
    Abstract: A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 11, 2024
    Inventors: Bharat Bhushan, Akshay N. Singh, Kunal R. Parekh
  • Publication number: 20230395545
    Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Bharat Bhushan, Akshay N. Singh, Bret K. Street, Debjit Datta, Eiichi Nakano
  • Publication number: 20230315545
    Abstract: Disclosed are techniques for function-defined output streams corresponding to combinations of events published to one or more event notification streams in an event-driven architecture with a plurality of event notification streams. An output function is received defining a combination of event notifications with criteria for selecting which event notifications to combine from one or more event notification streams. The one or more event notification streams are parsed, and event notifications are selected to initialize a new event notification stream, where event notifications in this stream correspond to instances of the output function when provided a set of event notifications from the one or more event notification streams as input values. When an event notification is published to the one or more event notification streams meeting the criteria specified in the output function, the new event notification stream publishes an event notification corresponding to an output value from the output function.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Bharat Bhushan, KAWEEPOJ PHACHARINTANAKUL, Wolfgang von Drews, Matthew Whitehead
  • Publication number: 20230309642
    Abstract: A ratchet mechanism for a hard hat and method of assembling the same are provided. The ratchet mechanism includes a knob with knob protrusions. The ratchet mechanism also includes a ratchet gear. The ratchet gear includes teeth engagement mechanisms. Each teeth engagement mechanism includes a hooking mechanism and a tooth protrusion. Each hooking mechanism is configured to engage with the knob protrusions. The ratchet mechanism also includes a band housing configured to allow a band to ratchetably move within the housing. The band housing also includes a knob engagement protrusion and a ratchet gear aperture configured with one or more teeth defining a ramped surface. The ratchet gear is disposed on the knob engagement protrusion and includes one or more ratchet gear teeth configured to engage with a set of band teeth on the band, such that the rotation of the ratchet gear tightens or loosens the band during operation.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Durgam GANGADHAR, Bharat Bhushan ARORA, Swapnil Gopal PATIL
  • Patent number: 11769756
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: September 26, 2023
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11712082
    Abstract: A ratchet mechanism for a hard hat and method of assembling the same are provided. The ratchet mechanism includes a knob with knob protrusions. The ratchet mechanism also includes a ratchet gear. The ratchet gear includes teeth engagement mechanisms. Each teeth engagement mechanism includes a hooking mechanism and a tooth protrusion. Each hooking mechanism is configured to engage with the knob protrusions. The ratchet mechanism also includes a band housing configured to allow a band to ratchetably move within the housing. The band housing also includes a knob engagement protrusion and a ratchet gear aperture configured with one or more teeth defining a ramped surface. The ratchet gear is disposed on the knob engagement protrusion and includes one or more ratchet gear teeth configured to engage with a set of band teeth on the band, such that the rotation of the ratchet gear tightens or loosens the band during operation.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: August 1, 2023
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Durgam Gangadhar, Bharat Bhushan Arora, Swapnil Gopal Patil
  • Patent number: 11678483
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Chris M. Carlson, Collin Howder
  • Patent number: 11675667
    Abstract: One example method includes performing data protection operations including backup operations. Backups of an availability group include a full backup, transaction log backups, and differential backups. Each differential backup includes transactions since the full backup. The differential backups are performed based on a trigger and, during a restore operation, the differential backups reduce the number of restores that need to be performed and can be restored instead of restoring the corresponding transactional log backups.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: June 13, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Bharat Bhushan, Niketan Narayan Kalaskar
  • Patent number: 11672114
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, David Daycock, Subramanian Krishnan, Leroy Ekarista Wibowo