Abstract: A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.

Abstract: A personal hygiene capsule has a housing. a toilet. at least one spray nozzle. a drain provided in a lower portion of the housing. and at least one scrub brush operably mounted to wash at least a portion of an occupant of the personal hygiene capsule. Methods of using the personal hygiene capsule are provided.

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

Abstract: Methods, systems, and devices for techniques for semiconductor die coupling in stacked memory architectures are described. A semiconductor system may include a semiconductor unit formed by multiple semiconductor dies, where each semiconductor die may be fabricated to be individually separable. Each semiconductor die may include a respective portion of circuitry associated with the semiconductor unit. The multiple semiconductor dies may be coupled with a carrier, and each semiconductor die may be coupled (e.g., electrically, communicatively) with at least one other semiconductor die. At least some of the semiconductor dies may be coupled with a respective set of one or more memory arrays, where each memory array may be operable based on the coupling between the multiple semiconductor dies.

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die, and a second plurality of stacked memory dies mounted on and electrically coupled with the first plurality of stacked memory dies. A first dielectric material is disposed around the first plurality of stacked memory dies. A second dielectric material is disposed at the first dielectric material and surrounding the second plurality of stacked memory dies. A third dielectric material is disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies and between the first dielectric material and the second dielectric material.

Abstract: A method of forming a semiconductor wafer is provided. The method includes dicing wafers into dies, testing the dies for known good dies, and bonding known good dies to a carrier wafer to form a top KGD wafer. The method also includes filling gaps between top dies to form a top gap-fill layer around and above each of the top dies, and bonding the top dies with a dummy silicon wafer. The method also includes bonding known good dies to carrier wafers to form one or more core KGD wafers, as well as filling gaps between the core dies to form a core gap-fill layer around each of the core dies. The method then includes bonding the one or more core KGD wafers to the top KGD wafer to form a KGD wafer stack.

Abstract: Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.

Abstract: A semiconductor device assembly with layered dielectric is disclosed. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die coupled with the first semiconductor die. The second semiconductor die is at least partially surrounded by a tensile dielectric and a compressive dielectric disposed at the first semiconductor die. The tensile dielectric is configured to experience tensile stress at an upper surface and compressive stress at a lower surface (e.g., the tensile dielectric will warp concave down). In contrast, the compressive dielectric is configured to experience compressive stress at an upper surface and tensile stress at a lower surface (e.g., the compressive dielectric will warp concave up). As a result, stress in the semiconductor device assembly can be reduced and overall yield can be improved.

Abstract: Disclosed are techniques for function-defined output streams corresponding to combinations of events published to one or more event notification streams in an event-driven architecture with a plurality of event notification streams. An output function is received defining a combination of event notifications with criteria for selecting which event notifications to combine from one or more event notification streams. The one or more event notification streams are parsed, and event notifications are selected to initialize a new event notification stream, where event notifications in this stream correspond to instances of the output function when provided a set of event notifications from the one or more event notification streams as input values. When an event notification is published to the one or more event notification streams meeting the criteria specified in the output function, the new event notification stream publishes an event notification corresponding to an output value from the output function.

Abstract: A semiconductor device is provided. The semiconductor device includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die at a first location above a back side surface of the logic die, a second plurality of stacked memory dies electrically coupled with the logic die at a second location above the back side surface of logic die, a first dielectric material disposed above the back side surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies, and a dummy die disposed above the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to back side surfaces of the first plurality and second plurality of stacked memory dies through a second dielectric layer having dielectric-dielectric fusion bonding.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A through via extends entirely through the substrate. The through via includes a protruding portion that extends beyond the back side of the substrate. A layer of silicon carbon nitride is disposed at the back side of the substrate and along sidewalls of the protruding portion of the through via. A layer of oxide is disposed at the back side of the substrate and at least partially surrounding the protruding portion of the through via. A conductive pad is disposed at a coupling surface of the through via and at least partially extending through the layer of oxide. As a result, a reliable and cost-efficient semiconductor device can be assembled.

Abstract: A semiconductor device with a through dielectric via is disclosed. The semiconductor device assembly can include a semiconductor die and multiple stacks of semiconductor dies coupled with the semiconductor die at different lateral locations. Dielectric material can be disposed at the semiconductor die between the multiple stacks of semiconductor dies. The through dielectric via can extend entirely through the dielectric material to the semiconductor die such that the through dielectric via couples with circuitry at the semiconductor die. In this way, the through dielectric via can provide power to the semiconductor die (e.g., exclusive of the multiple stacks of semiconductor dies).

Abstract: A semiconductor device is provided. The semiconductor device can have a front side at which circuitry is disposed. The circuitry can include a pad and a plurality of lines. A first layer of dielectric material can be disposed at the front side at least partially over the pad and the plurality of lines. A second layer of dielectric material can be disposed at the front side at least partially over the first layer of dielectric material. A dual damascene pad can extend through the first layer of dielectric material and the second layer of dielectric material to the pad. A dummy pad can be disposed in the second layer of dielectric material above the plurality of lines and spaced from the dual damascene pad. In doing so, a reliable semiconductor device can be implemented.

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a top memory die, and a one or more intermediate memory dies between the top memory die and the logic die. Front sides of the one or more intermediate memory dies at which active circuitry is disposed face a front side of the top memory die. Back sides of the one or more intermediate memory dies opposite the front sides face a back side of the logic die. In doing so, a cost-efficient, low-complexity semiconductor device can be assembled.

Abstract: A semiconductor device assembly, including a semiconductor die having a frontside surface, a first plurality of bond pads at the frontside surface and a first dielectric layer at the frontside surface; and an interface die having a frontside surface and a backside surface, the interface die including a second plurality of bond pads and a second dielectric layer disposed on the backside surface of the interface die, a third dielectric layer disposed on the frontside surface of the interface die, wherein the third dielectric layer includes a mechanically altered surface opposite the frontside surface of the interface die, and a redistribution layer disposed on the third dielectric layer and above the frontside surface of the interface die, wherein hybrid bonds are disposed between the frontside surface of the semiconductor die and the backside surface of the interface die.

Abstract: A determination is made that a backup of a database in an availability group provided by a relational database management system (RDBMS) should be performed. The availability group includes a node functioning as a primary node and hosting a primary replica of the database and one or more other nodes functioning as secondary nodes and hosting secondary replicas of the database. The availability group is a clusterless availability group in which the one or more other nodes functioning as secondary nodes are not available as automatic failover targets should the primary node become unavailable. A command is issued to a node in the availability group to obtain a globally unique identifier (GUID) of the availability group. The node is instructed to index a backup of the database against the GUID of the availability group.

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.

Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.

Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.