Patents by Inventor Bharat Bhushan

Bharat Bhushan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11876068
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: January 16, 2024
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20240014170
    Abstract: A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 11, 2024
    Inventors: Bharat Bhushan, Akshay N. Singh, Kunal R. Parekh
  • Publication number: 20230395545
    Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Bharat Bhushan, Akshay N. Singh, Bret K. Street, Debjit Datta, Eiichi Nakano
  • Publication number: 20230309642
    Abstract: A ratchet mechanism for a hard hat and method of assembling the same are provided. The ratchet mechanism includes a knob with knob protrusions. The ratchet mechanism also includes a ratchet gear. The ratchet gear includes teeth engagement mechanisms. Each teeth engagement mechanism includes a hooking mechanism and a tooth protrusion. Each hooking mechanism is configured to engage with the knob protrusions. The ratchet mechanism also includes a band housing configured to allow a band to ratchetably move within the housing. The band housing also includes a knob engagement protrusion and a ratchet gear aperture configured with one or more teeth defining a ramped surface. The ratchet gear is disposed on the knob engagement protrusion and includes one or more ratchet gear teeth configured to engage with a set of band teeth on the band, such that the rotation of the ratchet gear tightens or loosens the band during operation.
    Type: Application
    Filed: June 8, 2023
    Publication date: October 5, 2023
    Inventors: Durgam GANGADHAR, Bharat Bhushan ARORA, Swapnil Gopal PATIL
  • Publication number: 20230315545
    Abstract: Disclosed are techniques for function-defined output streams corresponding to combinations of events published to one or more event notification streams in an event-driven architecture with a plurality of event notification streams. An output function is received defining a combination of event notifications with criteria for selecting which event notifications to combine from one or more event notification streams. The one or more event notification streams are parsed, and event notifications are selected to initialize a new event notification stream, where event notifications in this stream correspond to instances of the output function when provided a set of event notifications from the one or more event notification streams as input values. When an event notification is published to the one or more event notification streams meeting the criteria specified in the output function, the new event notification stream publishes an event notification corresponding to an output value from the output function.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Inventors: Bharat Bhushan, KAWEEPOJ PHACHARINTANAKUL, Wolfgang von Drews, Matthew Whitehead
  • Patent number: 11769756
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: September 26, 2023
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11712082
    Abstract: A ratchet mechanism for a hard hat and method of assembling the same are provided. The ratchet mechanism includes a knob with knob protrusions. The ratchet mechanism also includes a ratchet gear. The ratchet gear includes teeth engagement mechanisms. Each teeth engagement mechanism includes a hooking mechanism and a tooth protrusion. Each hooking mechanism is configured to engage with the knob protrusions. The ratchet mechanism also includes a band housing configured to allow a band to ratchetably move within the housing. The band housing also includes a knob engagement protrusion and a ratchet gear aperture configured with one or more teeth defining a ramped surface. The ratchet gear is disposed on the knob engagement protrusion and includes one or more ratchet gear teeth configured to engage with a set of band teeth on the band, such that the rotation of the ratchet gear tightens or loosens the band during operation.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: August 1, 2023
    Assignee: HONEYWELL INTERNATIONAL INC.
    Inventors: Durgam Gangadhar, Bharat Bhushan Arora, Swapnil Gopal Patil
  • Patent number: 11675667
    Abstract: One example method includes performing data protection operations including backup operations. Backups of an availability group include a full backup, transaction log backups, and differential backups. Each differential backup includes transactions since the full backup. The differential backups are performed based on a trigger and, during a restore operation, the differential backups reduce the number of restores that need to be performed and can be restored instead of restoring the corresponding transactional log backups.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: June 13, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Bharat Bhushan, Niketan Narayan Kalaskar
  • Patent number: 11678483
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: June 13, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Chris M. Carlson, Collin Howder
  • Patent number: 11672114
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: June 6, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, David Daycock, Subramanian Krishnan, Leroy Ekarista Wibowo
  • Patent number: 11659448
    Abstract: This disclosure provides methods, devices and systems for controlling basic service set (BSS) configuration of an access point (AP) in a multi-AP network. The multi-AP network may include a first AP that manages a first basic service set (BSS) and a second AP that manages a second BSS. The first BSS and the second BSS may share one or more wireless channels or may have overlapping coverage areas. A multi-AP controller may determine a BSS configuration policy (such as a maximum transmission opportunity (TXOP) duration) for the second BSS based on a type of traffic in the first BSS. This disclosure includes techniques for sharing traffic characteristics, determining the BSS configuration policy, communicating the BSS configuration policy, and controlling the BSS configuration policies for multiple BSSs so that one of the BSSs can provide a quality of service (QoS) for one or more stations (STAs).
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 23, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaolong Huang, Srinivas Katar, Bharat Bhushan
  • Patent number: 11599428
    Abstract: A determination is made that a relational database management system (RDBMS) is configured as a distributed availability group. The distributed availability group spans first and second availability groups. Each availability group includes a cluster of servers hosting replicas of a database. One of the first or second availability groups functions as a primary availability group. Another of the first or second availability groups functions as a secondary availability group that is available as a failover target should the primary availability group become unavailable. A name of the distributed availability group is obtained. A first server in the first availability group is directed to backup a replica of the database being hosted by the first server. The directing includes instructing the first server to index the backup against the name of the distributed availability group.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: March 7, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Roland Anthony Fernandes, Bharat Bhushan
  • Publication number: 20230048311
    Abstract: Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.
    Type: Application
    Filed: February 7, 2022
    Publication date: February 16, 2023
    Inventors: Bharat Bhushan, Akshay N. Singh, Keizo Kawakita, Bret K. Street
  • Publication number: 20230026960
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 26, 2023
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20220406450
    Abstract: The invention relates to a novel method for scoring sleep stages of a mammal subject, comprising extracting features from polysomnography data using the continuous wavelet transform; grouping the extracted features into clusters that are assigned to different sleep stages; and scoring the sleep stages based on the clusters. The method does not require prior visual knowledge of sleep stages nor supervised training.
    Type: Application
    Filed: November 23, 2020
    Publication date: December 22, 2022
    Inventors: Claus-Peter Richter, Minh Ha Tran, Bharat Bhushan
  • Patent number: 11502053
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20220327025
    Abstract: One example method includes performing data protection operations including backup operations. Backups of an availability group include a full backup, transaction log backups, and differential backups. Each differential backup includes transactions since the full backup. The differential backups are performed based on a trigger and, during a restore operation, the differential backups reduce the number of restores that need to be performed and can be restored instead of restoring the corresponding transactional log backups.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 13, 2022
    Inventors: Bharat Bhushan, Niketan Narayan Kalaskar
  • Publication number: 20220328456
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Application
    Filed: June 27, 2022
    Publication date: October 13, 2022
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11450645
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11438801
    Abstract: Certain aspects relate to methods and apparatus for traffic separation in a multi AP (MAP) network. In some cases, a MAP Controller may configure sets of SSIDs to a single VLAN ID in a Traffic Separation Policy and distribute the Traffic Separation Policy information to the MAP Agents.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 6, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaolong Huang, Bharat Bhushan, Brian Michael Buesker, Sai Yiu Duncan Ho