Patents by Inventor Bharat Bhushan

Bharat Bhushan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11450645
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: September 20, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11438801
    Abstract: Certain aspects relate to methods and apparatus for traffic separation in a multi AP (MAP) network. In some cases, a MAP Controller may configure sets of SSIDs to a single VLAN ID in a Traffic Separation Policy and distribute the Traffic Separation Policy information to the MAP Agents.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: September 6, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaolong Huang, Bharat Bhushan, Brian Michael Buesker, Sai Yiu Duncan Ho
  • Publication number: 20220229740
    Abstract: A determination is made that a relational database management system (RDBMS) is configured as a distributed availability group. The distributed availability group spans first and second availability groups. Each availability group includes a cluster of servers hosting replicas of a database. One of the first or second availability groups functions as a primary availability group. Another of the first or second availability groups functions as a secondary availability group that is available as a failover target should the primary availability group become unavailable. A name of the distributed availability group is obtained. A first server in the first availability group is directed to backup a replica of the database being hosted by the first server. The directing includes instructing the first server to index the backup against the name of the distributed availability group.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 21, 2022
    Inventors: Roland Anthony Fernandes, Bharat Bhushan
  • Publication number: 20220229741
    Abstract: A determination is made that a backup of a database in an availability group provided by a relational database management system (RDBMS) should be performed. The availability group includes a node functioning as a primary node and hosting a primary replica of the database and one or more other nodes functioning as secondary nodes and hosting secondary replicas of the database. The availability group is a clusterless availability group in which the one or more other nodes functioning as secondary nodes are not available as automatic failover targets should the primary node become unavailable. A command is issued to a node in the availability group to obtain a globally unique identifier (GUID) of the availability group. The node is instructed to index a backup of the database against the GUID of the availability group.
    Type: Application
    Filed: January 21, 2021
    Publication date: July 21, 2022
    Inventors: Bharat Bhushan, Niketan Kalaskar
  • Publication number: 20220218717
    Abstract: The present invention relates to soft chewable composition and its method of manufacturing using pharmaceutical conventional equipment. The present invention relates to process for manufacturing soft chewable dosage form by manufacturing free flowing soft chewable granules and these granules are compressed to make soft chewable tablets using rotary compression machine. The free-flowing granules of the invention are formed of active ingredients or nutritional agents, diluents, binder, disintegrant, sugar component, oil component or humectant or combination of both, flavour, lubricant or plasticizers in intragranular or extra granular and other conventional tableting aids to help in making the tablet more palatable.
    Type: Application
    Filed: May 17, 2020
    Publication date: July 14, 2022
    Inventors: Vishal OHLAN, Bharat Bhushan SANDUJA
  • Publication number: 20220165701
    Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal, David A. Daycock
  • Publication number: 20220165708
    Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Bharat Bhushan, Pratap Murali, Raj K. Bansal
  • Patent number: 11310690
    Abstract: Certain aspects relate to methods and apparatus for traffic flow service prioritization in a multi AP (MAP) network.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 19, 2022
    Assignee: QUALCOMM INCORPORATED
    Inventors: Xiaolong Huang, Bharat Bhushan, Brian Michael Buesker, Sai Yiu Duncan Ho
  • Patent number: 11248129
    Abstract: Articles including repellent surfaces and methods of making and using these articles are disclosed. The repellant surface can comprise a polymer having a roughened surface and a fluorinated silane and a lubricating liquid deposited on the roughened surface. The repellent surface, and by extension the articles described herein, can exhibit superomniphobic properties. The methods for producing the repellant surface can comprise dissolving a polymer in a solvent to produce a polymer solution and optionally adding a non-solvent to the polymer solution to produce a casting mixture. The polymer solution or casting mixture can be deposited on a surface of a substrate and the solvent and/or the non-solvent evaporated to provide a coated-substrate having a roughened surface. A functional layer comprising a fluorinated silane followed by a lubricating liquid can be deposited on the roughened surface to form the repellant surface.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 15, 2022
    Assignee: Ohio State Innovation Foundation
    Inventors: Philip Simon Brown, Bharat Bhushan
  • Publication number: 20220022809
    Abstract: A sleep monitor device for monitoring breathing and other physiological parameters is used to classify, assess, diagnose, and/or treat sleeping disorders (e.g., obstructive sleep apnea and upper airway obstruction, among others). The sleep monitor device can be a wearable device that contains one or more microphones arranged around the subject's neck when worn. Additionally, the wearable device may also include, or otherwise be in communication with, other sensors and/or measurement components, such as optical sources and electrodes. Using the sleep monitor device it is possible to identify upper airway resistances, the site of the obstruction, to monitor tissue resistance, temperature, and oxygen saturation. Early detection of the development of upper airway resistances during sleep can be used to control supportive measures for sleep apnea, such controlling continuous positive airway pressure (“CPAP”) devices or neurological or mechanical stimulators.
    Type: Application
    Filed: December 19, 2019
    Publication date: January 27, 2022
    Inventors: Bharat Bhushan, Claus-Peter Richter, Amedee Brennan O'Gorman
  • Publication number: 20210375902
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.
    Type: Application
    Filed: August 9, 2021
    Publication date: December 2, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Bharat Bhushan, David Daycock, Subramanian Krishnan, Leroy Ekarista Wibowo
  • Patent number: 11174397
    Abstract: Provided herein are articles including repellent coatings, as well as methods of making as using these articles. The articles can comprise a substrate and a repellent coating disposed on a surface of the substrate. The repellant coating can comprise hydrophobic particles dispersed within a polymer binder. The hydrophobic particles can be aggregated within the polymer binder, thereby forming a multiplicity of re-entrant structures embedded within and protruding from the polymer binder. The repellent coatings, and by extension the articles described herein, can exhibit selective wetting properties (e.g., superhydrophilicty/super-oleophobicity, or super-hydrophobicity/superoleophilicity).
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 16, 2021
    Assignee: Ohio State Innovation Foundation
    Inventors: Samuel Graeme Martin, Philip Simon Brown, Bharat Bhushan
  • Patent number: 11177269
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Chris M. Carlson, Collin Howder
  • Patent number: 11146678
    Abstract: The exemplary embodiments disclose a system and method, a computer program product, and a computer system for determining the context of calls and providing a user interface to a user. The exemplary embodiments may include collecting data from the call, extracting one or more features from the collected data, determining a context of the call based on applying one or more models to the extracted one or more features, and providing a user with a user interface.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Raghuveer Prasad Nagar, Manjit Singh Sodhi, Bharat Bhushan Balothia
  • Patent number: 11134449
    Abstract: This disclosure provides systems, methods and apparatuses, including computer programs encoded on computer-readable media, for controlling transmission power in a network having multiple access points (APs). In one aspect, by enabling control of transmission power adjustment operations, APs can effectively delivery data to stations (STAs) within the basis service set (BSS) in a manner that minimizes co-channel interference between nearby APs in the network. The transmission power adjustment operations may be used to generate an interference reduction plan that accounts for some or all of the traffic patterns in the network, the capacities of the APs in the network and the service needs of all the STAs in the network. In this manner, APs are afforded a more lenient approach to adequately delivering data to STAs within the BSS, while mitigating interference with other APs or STAs operating in nearby wireless coverage areas.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 28, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Bhushan, Avneet Kaur Puri
  • Patent number: 11121144
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Bharat Bhushan, David Daycock, Subramanian Krishnan, Leroy Ekarista Wibowo
  • Publication number: 20210266402
    Abstract: The exemplary embodiments disclose a system and method, a computer program product, and a computer system for determining the context of calls and providing a user interface to a user. The exemplary embodiments may include collecting data from the call, extracting one or more features from the collected data, determining a context of the call based on applying one or more models to the extracted one or more features, and providing a user with a user interface.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Inventors: Raghuveer Prasad Nagar, Manjit Singh Sodhi, Bharat Bhushan Balothia
  • Publication number: 20210219647
    Abstract: A ratchet mechanism for a hard hat and method of assembling the same are provided. The ratchet mechanism includes a knob with knob protrusions. The ratchet mechanism also includes a ratchet gear. The ratchet gear includes teeth engagement mechanisms. Each teeth engagement mechanism includes a hooking mechanism and a tooth protrusion. Each hooking mechanism is configured to engage with the knob protrusions. The ratchet mechanism also includes a band housing configured to allow a band to ratchetably move within the housing. The band housing also includes a knob engagement protrusion and a ratchet gear aperture configured with one or more teeth defining a ramped surface. The ratchet gear is disposed on the knob engagement protrusion and includes one or more ratchet gear teeth configured to engage with a set of band teeth on the band, such that the rotation of the ratchet gear tightens or loosens the band during operation.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 22, 2021
    Inventors: Durgam GANGADHAR, Bharat Bhushan ARORA, Swapnil Gopal PATIL
  • Patent number: 11018093
    Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 25, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Bharat Bhushan, Juan Boon Tan, Boo Yang Jung, Wanbing Yi, Danny Pak-Chum Shum
  • Publication number: 20210151454
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Bharat Bhushan, Chris M. Carlson, Collin Howder