Patents by Inventor Bharat Sukhwani
Bharat Sukhwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9495418Abstract: Embodiments include methods, systems and computer program products for offloading multiple processing operations to an accelerator. Aspects include receiving a database query from an application, performing an analysis on the query, and identifying a plurality of available accelerators. Aspects further include retrieving cost information for one or more templates available on each of the plurality of available accelerators, determining a query execution plan based on the cost information and the analysis on the query, and offloading one or more query operations to at least one of the plurality of accelerators based on the query execution plan.Type: GrantFiled: August 7, 2013Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sameh W. Asaad, Parijat Dube, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Publication number: 20160292201Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.Type: ApplicationFiled: March 30, 2015Publication date: October 6, 2016Inventors: Sameh W. Asaad, Robert J. Halstead, Bharat Sukhwani
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Publication number: 20160292209Abstract: Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.Type: ApplicationFiled: July 6, 2015Publication date: October 6, 2016Inventors: Sameh W. Asaad, Robert J. Halstead, Bharat Sukhwani
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Patent number: 9448845Abstract: Embodiments include methods, systems and computer program products for providing an extendable job structure for executing instructions on an accelerator. The method includes creating a number of data descriptor blocks, each memory location addresses and a pointer to a next of the number of the data descriptor block. The method further includes creating a last data descriptor block having memory location addresses and a last block indicator. Based on determining that additional memory is required for executing instructions on the accelerator, the method includes modifying the last data descriptor block to become a data extender block having a pointer to one of one or more new data descriptor blocks and creating a new last data descriptor block.Type: GrantFiled: April 7, 2016Date of Patent: September 20, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sameh W. Asaad, Parijat Dube, Hong Min, Donald W. Schmidt, Bharat Sukhwani, Mathew S. Thoennes
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Publication number: 20160224268Abstract: Embodiments include methods, systems and computer program products for providing an extendable job structure for executing instructions on an accelerator. The method includes creating a number of data descriptor blocks, each memory location addresses and a pointer to a next of the number of the data descriptor block. The method further includes creating a last data descriptor block having memory location addresses and a last block indicator. Based on determining that additional memory is required for executing instructions on the accelerator, the method includes modifying the last data descriptor block to become a data extender block having a pointer to one of one or more new data descriptor blocks and creating a new last data descriptor block.Type: ApplicationFiled: April 7, 2016Publication date: August 4, 2016Inventors: Sameh W. Asaad, Parijat Dube, Hong Min, Donald W. Schmidt, Bharat Sukhwani, Mathew S. Thoennes
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Publication number: 20160188644Abstract: Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator having an external memory. The method includes receiving a plurality of key values by the hardware accelerator, assigning each of the plurality of key values a sequential key number as the plurality of key values are received and performing pairwise comparisons of each of the plurality of key values to identify a winning key and a losing key. The method also includes storing the losing key of each pairwise comparison in a first section of the external memory, wherein a location in the first section is based on the key number of the losing key and storing the winning key of each pairwise comparison in a second section of the external memory, wherein a location in the second section is based on the key number of the winning key.Type: ApplicationFiled: June 17, 2015Publication date: June 30, 2016Inventors: BHARAT SUKHWANI, MATHEW S. THOENNES
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Publication number: 20160188294Abstract: Embodiments include methods, systems and computer program products for performing a tournament tree sort on a hardware accelerator having an external memory. The method includes receiving a plurality of key values by the hardware accelerator, assigning each of the plurality of key values a sequential key number as the plurality of key values are received and performing pairwise comparisons of each of the plurality of key values to identify a winning key and a losing key. The method also includes storing the losing key of each pairwise comparison in a first section of the external memory, wherein a location in the first section is based on the key number of the losing key and storing the winning key of each pairwise comparison in a second section of the external memory, wherein a location in the second section is based on the key number of the winning key.Type: ApplicationFiled: December 29, 2014Publication date: June 30, 2016Inventors: BHARAT SUKHWANI, MATHEW S. THOENNES
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Patent number: 9336056Abstract: Embodiments include methods, systems and computer program products for providing an extendable job structure for executing instructions on an accelerator. The method includes creating a number of data descriptor blocks, each having a fixed number of memory location addresses and a pointer to a next of the number of the data descriptor block. The method further includes creating a last data descriptor block having the fixed number of memory location addresses and a last block indicator. Based on determining that additional memory is required for executing instructions on the accelerator, the method includes modifying the last data descriptor block to become a data extender block having a pointer to one of one or more new data descriptor blocks and creating a new last data descriptor block.Type: GrantFiled: December 31, 2013Date of Patent: May 10, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sameh W. Asaad, Parijat Dube, Hong Min, Donald W. Schmidt, Bharat Sukhwani, Mathew S. Thoennes
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Patent number: 9336274Abstract: Embodiments include methods, systems and computer program products for offloading multiple processing operations to an accelerator. Aspects include receiving a database query from an application, performing an analysis on the query, and identifying a plurality of available accelerators. Aspects further include retrieving cost information for one or more templates available on each of the plurality of available accelerators, determining a query execution plan based on the cost information and the analysis on the query, and offloading one or more query operations to at least one of the plurality of accelerators based on the query execution plan.Type: GrantFiled: September 5, 2013Date of Patent: May 10, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sameh W. Asaad, Parijat Dube, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Publication number: 20160110395Abstract: Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys.Type: ApplicationFiled: December 22, 2015Publication date: April 21, 2016Inventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Publication number: 20160110390Abstract: Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys.Type: ApplicationFiled: December 22, 2015Publication date: April 21, 2016Inventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Patent number: 9317497Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method includes determining that a database query warrants a first projection operation to project a plurality of input rows to a plurality of projected rows, where each of the plurality of input rows has one or more variable-length columns. A first projection control block is constructed, by a computer processor, to describe the first projection operation. The first projection operation is offloaded to a hardware accelerator. The first projection control block is provided to the hardware accelerator, and the first projection control block enables the hardware accelerator to perform the first projection operation at streaming rate.Type: GrantFiled: August 20, 2013Date of Patent: April 19, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sameh W. Asaad, Parijat Dube, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Patent number: 9275168Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method includes receiving, at a hardware accelerator, a first instruction to project a first plurality of database rows, where each of the first plurality of database rows has one or more variable-length columns. The first plurality of database rows are projected, by a computer processor, to produce a first plurality of projected rows. This projection is performed at streaming rate.Type: GrantFiled: July 19, 2013Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Sameh W. Assad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Patent number: 9268879Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method includes receiving, at a hardware accelerator, a first instruction to project a first plurality of database rows, where each of the first plurality of database rows has one or more variable-length columns. The first plurality of database rows are projected, by a computer processor, to produce a first plurality of projected rows. This projection is performed at streaming rate.Type: GrantFiled: August 20, 2013Date of Patent: February 23, 2016Assignee: International Business Machines CorporationInventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Patent number: 9251218Abstract: Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys.Type: GrantFiled: August 7, 2013Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Patent number: 9251219Abstract: Embodiments include methods, systems and computer program products for performing a composite sort on a tunable hardware sort engine includes determining desired sort performance parameters, configuring a composite sort engine based on the desired sort performance parameters, and receiving a plurality of keys having a payload associated with each of the plurality of keys. The method also includes reserving DRAM storage for each of the payloads, generating a tag for each of the plurality of keys, the tag identifying the DRAM storage reserved for each of the payloads, and storing the payloads in the portions of the DRAM storage. The method further includes generating a composite key for each of the plurality of keys, sorting the composite keys by the composite sort engine, and retrieving the payloads associated with the sorted composite keys from the DRAM storage. The method also includes outputting the payloads associated the sorted composite keys.Type: GrantFiled: September 5, 2013Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Publication number: 20160019262Abstract: In some embodiments, a query recipient is configured to determine that a database query warrants a first projection operation to project a plurality of input rows to a plurality of projected rows. Each of the input rows has one or more variable-length columns. A projection controller is configured to construct a first projection control block to describe the first projection operation. For this construction, the projection controller is configured to construct a plurality of projection control elements, each one corresponding to a corresponding column in the input rows, and a header to specify the order of the projection control elements. The projection controller is further configured to offload the first projection operation to a hardware accelerator, and to provide the first projection control block to the hardware accelerator, where the first projection control block enables the hardware accelerator to perform the first projection operation at streaming rate.Type: ApplicationFiled: September 29, 2015Publication date: January 21, 2016Inventors: Sameh W. Asaad, Parijat Dube, Hong Min, Bharat Sukhwani, Matthew S. Thoennes
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Publication number: 20160012107Abstract: Methods and arrangements for mapping a query operation to an accelerator are provided. The method includes receiving, by a processor, a query operation and determining the design logic of the query operation, receiving a configuration of one or more available accelerators and a design logic of each of the one or more available accelerators, and determining if the query operation can be offloaded to one or more of the one or more available accelerators. Based on a determination that the query operation can be offloaded to one or more of the one or more available accelerators, the method also includes creating software structures to interface with a selected accelerator and executing the query operation on the selected accelerator. Based on a determination that the query operation cannot be offloaded to one or more of the one or more available accelerators, the method further includes executing the query operation in software.Type: ApplicationFiled: July 11, 2014Publication date: January 14, 2016Inventors: Sameh Asaad, Parijat Dube, Balakrishna R. Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Patent number: 9235564Abstract: In an exemplary embodiment of this disclosure, a computer-implemented method includes determining that a database query warrants a first projection operation to project a plurality of input rows to a plurality of projected rows, where each of the plurality of input rows has one or more variable-length columns. A first projection control block is constructed, by a computer processor, to describe the first projection operation. The first projection operation is offloaded to a hardware accelerator. The first projection control block is provided to the hardware accelerator, and the first projection control block enables the hardware accelerator to perform the first projection operation at streaming rate.Type: GrantFiled: July 19, 2013Date of Patent: January 12, 2016Assignee: International Business Machines CorporationInventors: Sameh W. Asaad, Parijat Dube, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
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Patent number: 9177006Abstract: Methods and arrangements for a radix sort with a read only key. A plurality of keys are received, an array and a link table are populated for the first digit of the keys based upon the keys; and an array and a link table are populated for each successive digit of the keys based upon the array and link table populated for the preceding digit of the keys. Embodiments may be implemented in both hardware (FPGAs, ASICs, information handling devices, etc.) and software. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 29, 2012Date of Patent: November 3, 2015Assignee: International Business Machines CorporationInventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes