Patents by Inventor Bharat Sukhwani

Bharat Sukhwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140188909
    Abstract: Methods and arrangements for a radix sort with a read only key. A plurality of keys are received, an array and a link table are populated for the first digit of the keys based upon the keys; and an array and a link table are populated for each successive digit of the keys based upon the array and link table populated for the preceding digit of the keys. Embodiments may be implemented in both hardware (FPGAs, ASICs, information handling devices, etc.) and software. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: February 8, 2013
    Publication date: July 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh W. Asaad, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Publication number: 20140067851
    Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Bernard V. Brezzo, Donna N. Eng Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Publication number: 20140067845
    Abstract: Methods and arrangements for facilitating accelerations of database functions. A field programmable gate array is incorporated. At least one query control block is incorporated in the field programmable gate array, and database management system operations are accelerated via the field programmable gate array. The accelerating includes employing the at least one query control block to execute a query without reconfiguring the field programmable gate array.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Bernard V. Brezzo, Donna N. Eng Dillenberger, Parijat Dube, Balakrishna Raghavendra Iyer, Hong Min, Bharat Sukhwani, Mathew S. Thoennes
  • Publication number: 20140032509
    Abstract: A method comprises streaming one or more pages of a database to a hardware accelerator, extracting one or more rows from each of the one or more pages of the database, determining whether a given one of the extracted rows is compressed, decompressing the given one of the extracted rows responsive to the determination and outputting the decompressed row. The decompressing step is performed in the hardware accelerator. The hardware accelerator may be a field-programmable gate array. The method allows for hardware accelerated row decompression.
    Type: Application
    Filed: August 24, 2012
    Publication date: January 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: BHARAT SUKHWANI, SAMEH ASAAD, BALAKRISHNA R. IYER, HONG MIN, MATHEW S. THOENNES
  • Publication number: 20140032516
    Abstract: An apparatus comprises a hardware accelerator coupled to a memory. The hardware accelerator comprises one or more decompression units. The one or more decompression units are reconfigurable. The hardware accelerator may be a field-programmable gate array. The hardware accelerator may also comprise one or more reconfigurable scanner units. The one or more decompression units, in the aggregate, are operative to decompress one or more rows of a database at a bus speed of the coupling between the hardware accelerator and the memory. Two or more decompression units are operative to decompress two or more rows of a database in parallel. The apparatus allows for hardware accelerated row decompression.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Bharat Sukhwani, Sameh Asaad, Balakrishna R. Iyer, Hong Min, Mathew S. Thoennes
  • Publication number: 20130318107
    Abstract: Generating a data feed specific parser circuit is provided. An input of a number of bytes of feed data associated with a particular data feed that the data feed specific parser circuit is to process is received. A feed format specification file that describes a data format of the particular data feed is parsed to generate an internal data structure of the feed format specification file. A minimum number of parallel pipeline stages in the data feed specific parser circuit to process the number of bytes of feed data associated with the particular data is determined based on the generated internal data structure of the feed format specification file. Then, a description of the data feed specific parser circuit with the determined number of parallel pipeline stages is generated.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Roger Moussalli, Bharat Sukhwani
  • Publication number: 20130318067
    Abstract: Techniques are provided for hardware-accelerated relational joins. A first table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the first table is hashed to set at least one bit in at least one bit vector. A second table comprising one or more rows is processed through a hardware accelerator. At least one join column in at least one of the one or more rows of the second table is hashed to generate at least one hash value. At least one bit vector is probed using the at least one hash value. A joined row is constructed responsive to the probing step. The row-construction step is performed in the hardware accelerator.
    Type: Application
    Filed: May 23, 2012
    Publication date: November 28, 2013
    Applicant: International Business Machines Corporation
    Inventors: Bharat Sukhwani, Sameh W. Asaad, Hong Min, Matthew S. Thoennes, Gong Su