Patents by Inventor Bi-Ming Yen

Bi-Ming Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9176388
    Abstract: Systems and methods are provided for forming features through photolithography. A polymer layer is formed over a substrate. The polymer layer is patterned to form a first feature and a second feature, the first feature and the second feature being separated at a first distance. A rinse material is applied to the polymer layer including the first feature and the second feature. The rinse material is removed from the polymer layer including the first feature and the second feature to cause the first feature and the second feature to come into contact with each other. A third feature is formed based on the first feature and the second feature being in contact with each other.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: November 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chun-Liang Tai, Bi-Ming Yen, Chun-Hung Lee, De-Fang Chen
  • Patent number: 9159581
    Abstract: This description relates to a method of making a semiconductor device including forming an inter-level dielectric (ILD) layer over a substrate and forming a layer set over the ILD layer. The method further includes etching the layer set to form a tapered opening in the layer set and etching the ILD layer using the layer set as a mask to form an opening in the ILD layer. The opening in the ILD layer has a line width roughness (LWR) of less than 3 nanometers (nm). This description also relates to a semiconductor device including an inter-level dielectric (ILD) layer over a substrate; and a layer set over the ILD layer. The layer set has a tapered opening within the layer set. Etching the layer set comprises forming the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from 85-degrees to 90-degrees.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: October 13, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsai-Chun Li, Bi-Ming Yen
  • Patent number: 9159580
    Abstract: A mechanism for forming a semiconductor device is described. The semiconductor device includes a substrate and an inter-layer dielectric (ILD) layer over the substrate. The intermediate semiconductor device further includes a first layer set over the ILD layer and a second layer set over the first layer set. The intermediate semiconductor device further includes a photoresist layer over the second layer set. The method further includes etching the second layer set to form a tapered opening in the second layer set, the tapered opening having sidewalls at an angle with respect to a top surface of the ILD layer ranging from about 85-degrees to about 90-degrees, but less than 90-degrees. The method further includes etching the first layer set to form an opening in the first layer set and etching the ILD layer using the first layer set as a mask to form an opening in the ILD layer.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 13, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bi-Ming Yen, Tsai-Chun Li, Chun-Ming Hu
  • Publication number: 20150125788
    Abstract: Systems and methods are provided for forming features through photolithography. A polymer layer is formed over a substrate. The polymer layer is patterned to form a first feature and a second feature, the first feature and the second feature being separated at a first distance. A rinse material is applied to the polymer layer including the first feature and the second feature. The rinse material is removed from the polymer layer including the first feature and the second feature to cause the first feature and the second feature to come into contact with each other. A third feature is formed based on the first feature and the second feature being in contact with each other.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHUN-LIANG TAI, BI-MING YEN, CHUN-HUNG LEE, DE-FANG CHEN
  • Patent number: 8912633
    Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 16, 2014
    Assignee: Lam Research Corporation
    Inventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
  • Patent number: 8801892
    Abstract: Etching a layer over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to the outer zone within the plasma processing chamber, where the outer zone surrounds the inner zone and the first gas is different than the second gas. Plasmas are simultaneously generated from the first gas and second gas. The layer is etched, where the layer is etched by the plasmas from the first gas and second gas.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: August 12, 2014
    Assignee: Lam Research Corporation
    Inventors: Dean J. Larson, Babak Kadkhodayan, Di Wu, Kenji Takeshita, Bi-Ming Yen, Xingcai Su, William M. Denty, Jr., Peter Loewenhardt
  • Patent number: 8652298
    Abstract: Methods, systems, and computer programs are presented for semiconductor manufacturing are provided. One wafer processing apparatus includes: a top electrode; a bottom electrode; a first radio frequency (RF) power source; a second RF power source; a third RF power source; a fourth RF power source; and a switch. The first, second, and third power sources are coupled to the bottom electrode. Further, the switch is operable to be in one of a first position or a second position, where the first position causes the top electrode to be connected to ground, and the second position causes the top electrode to be connected to the fourth RF power source.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 18, 2014
    Assignee: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Alexei Marakhtanov, Gerardo Delgadino, Eric Hudson, Bi Ming Yen, Andrew D. Bailey, III
  • Publication number: 20130126475
    Abstract: Methods, systems, and computer programs are presented for semiconductor manufacturing are provided. One wafer processing apparatus includes: a top electrode; a bottom electrode; a first radio frequency (RF) power source; a second RF power source; a third RF power source; a fourth RF power source; and a switch. The first, second, and third power sources are coupled to the bottom electrode. Further, the switch is operable to be in one of a first position or a second position, where the first position causes the top electrode to be connected to ground, and the second position causes the top electrode to be connected to the fourth RF power source.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 23, 2013
    Applicant: Lam Research Corporation
    Inventors: Rajinder Dhindsa, Alexei Marakhtanov, Gerardo Delgadino, Eric Hudson, Bi Ming Yen, Andrew D. Bailey, III
  • Publication number: 20130001754
    Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.
    Type: Application
    Filed: September 7, 2012
    Publication date: January 3, 2013
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
  • Patent number: 8283255
    Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: October 9, 2012
    Assignee: Lam Research Corporation
    Inventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
  • Patent number: 8236188
    Abstract: A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: August 7, 2012
    Assignee: Lam Research Corporation
    Inventors: Bing Ji, Kenji Takeshita, Andrew D. Bailey, III, Eric A. Hudson, Maryam Moravej, Stephen M. Sirard, Jungmin Ko, Daniel Le, Robert C. Hefty, Yu Cheng, Gerardo A. Delgadino, Bi-Ming Yen
  • Patent number: 7951616
    Abstract: A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: May 31, 2011
    Assignee: Lam Research Corporation
    Inventors: Keren J. Kanarik, C. Robert Koemtzopoulos, James Rogers, Bi Ming Yen
  • Publication number: 20100261352
    Abstract: A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.
    Type: Application
    Filed: April 7, 2010
    Publication date: October 14, 2010
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Bing Ji, Kenji Takeshita, Andrew D. Bailey, III, Eric A. Hudson, Maryam Moravej, Stephen M. Sirard, Jungmin Ko, Daniel Le, Robert C. Hefty, Yu Cheng, Gerardo A. Delgadino, Bi-Ming Yen
  • Patent number: 7789991
    Abstract: A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: September 7, 2010
    Assignee: Lam Research Corporation
    Inventors: Binet A. Worsham, Sean S. Kang, David Wei, Vinay Pohray, Bi Ming Yen
  • Publication number: 20100022033
    Abstract: A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber.
    Type: Application
    Filed: October 1, 2009
    Publication date: January 28, 2010
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Keren J. KANARIK, C. Robert KOEMTZOPOULOS, James ROGERS, Bi Ming YEN
  • Publication number: 20090020417
    Abstract: Methods of depositing a protective coating of a silicon-containing or metallic material onto a semiconductor substrate include sputtering such material from an electrode onto a semiconductor substrate in a plasma processing chamber. The protective material can be deposited onto a multi-layer mask overlying a low-k material and/or onto the low-k material. The methods can be used in dual damascene processes to protect the mask and enhance etch selectivity, to protect the low-k material from carbon depletion during resist strip processes, and/or protect the low-k material from absorption of moisture.
    Type: Application
    Filed: September 29, 2004
    Publication date: January 22, 2009
    Inventors: Jisoo Kim, Jong Shon, Bi Ming Yen, Peter Loewenhardt
  • Publication number: 20080293249
    Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 27, 2008
    Inventors: Sangjun Cho, Tom Choi, Taejoon Han, Sean Kang, Prabhakara Gopaladasu, Bi-Ming Yen
  • Patent number: 7442114
    Abstract: Methods for cleaning an electrode assembly, which can be used for etching a dielectric material in a plasma etching chamber after the cleaning, comprise polishing a silicon surface of the electrode assembly, preferably to remove black silicon contamination therefrom.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: October 28, 2008
    Assignee: Lam Research Corporation
    Inventors: Tuochuan Huang, Daxing Ren, Hong Shih, Catherine Zhou, Chun Yan, Enrico Magni, Bi Ming Yen, Jerome Hubacek, Dae J. Lim, Dougyong Sung
  • Publication number: 20080210377
    Abstract: Etching a layer over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to the outer zone within the plasma processing chamber, where the outer zone surrounds the inner zone and the first gas is different than the second gas. Plasmas are simultaneously generated from the first gas and second gas. The layer is etched, where the layer is etched by the plasmas from the first gas and second gas.
    Type: Application
    Filed: March 25, 2008
    Publication date: September 4, 2008
    Applicant: LAM RESEARCH CORPORATION
    Inventors: Dean J. Larson, Babak Kadkhodayan, Di Wu, Kenji Takeshita, Bi-Ming Yen, Xingcai Su, William M. Denty, Peter Loewenhardt
  • Patent number: 7371332
    Abstract: Etching a layer over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to the outer zone within the plasma processing chamber, where the outer zone surrounds the inner zone and the first gas is different than the second gas. Plasmas are simultaneously generated from the first gas and second gas. The layer is etched, where the layer is etched by the plasmas from the first gas and second gas.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: May 13, 2008
    Assignee: LAM Research Corporation
    Inventors: Dean J. Larson, Babak Kadkhodayan, Di Wu, Kenji Takeshita, Bi-Ming Yen, Xingcai Su, William M. Denty, Jr., Peter Loewenhardt