Abstract: Provided are a display substrate and a display apparatus. The display substrate includes a display region and a bonding region connected with the display region, the display region includes multiple data signal lines and K rows and L columns of sub-pixels; multiple first spaces are included between K sub-pixel rows, multiple second spaces are included between L sub-pixel columns, at least one first space is provided with a first data connection line, and at least one second space is provided with at least one second data connection line; one end of the first data connection line is electrically connected with one of the data signal lines, and the other end is electrically connected with one of second data connection lines; one end of the second data connection line is electrically connected with the first data connection line, and the other end is electrically connected with the bonding region.

Abstract: A method for improving digestion performance for proteins in food, and a protein composition and food containing same. According to the method, the content of ?-lactalbumin in food is controlled to be 10.5% to 51.0%, and the content of ?-casein is controlled to be 10.0% to 40.0%. Said contents are calculated on the basis that the total protein content in the food is 100%.

Abstract: Provided are a pixel circuit, a driving method and a display apparatus, including: a light emitting device; a driving transistor, configured to produce a current for driving the light emitting device to emit light according to a data voltage; a voltage control circuit, coupled to the driving transistor, wherein the voltage control circuit is configured to reset the driving transistor (M0) and input the data voltage in response to a loaded signal; and a light emitting control circuit, coupled to the driving transistor and the light emitting device, wherein the light emitting control circuit is configured to provide the current produced by the driving transistor to the light emitting device; wherein a frequency of resetting the driving transistor is not less than a frequency of inputting the data voltage.

Abstract: An array substrate is provided. The array substrate includes K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate. The K number of reset signal lines includes a plurality of third reset signal lines in (2k?1)-th columns of K columns, K and k being positive integers, 1?k?(K/2); and a plurality of fourth reset signal lines in (2k)-th columns of the K columns.

Abstract: A display substrate and a display device. In the display substrate, a plurality of first output ends of the plurality of straight edge gate driving structures are connected to the plurality of first signal lines through a plurality of first connection structures, and a plurality of second output ends of the plurality of rounded corner gate driving structures are connected to the plurality of second signal lines through a plurality of second connection structures; the first conductive part and the second conductive part are located in a same conductive layer, and a number and a type of the plurality of via connection structures in each of the plurality of first connection structures are the same as a number and a type of the plurality of via connection structures in each of the plurality of second connection structures.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, a pixel circuit layer and an anode layer; the pixel circuit layer includes a plurality of pixel driving circuits, the anode layer includes a plurality of anode groups, each of the plurality of anode groups includes a first anode and a second anode which are oppositely arranged, the first anode includes a first main body portion and a first connection portion, the first anode further includes an extension portion and an anode compensation portion, an orthographic projection of the anode compensation portion on the base substrate covers one thin film transistor in the pixel driving circuit connected to the first connection portion.

Abstract: A display panel and a display apparatus are provided. The display panel includes: first color sub-pixels in a first color sub-pixel column, second color sub-pixels in a second color sub-pixel column, and third color sub-pixels in a third color sub-pixel column; multiple data signal lines including a first data signal line connected to the first color sub-pixel column, a second data signal line connected to the second color sub-pixel column, and a third data signal line connected to the third color sub-pixel column; multiple compensation units including a first compensation capacitor connected to the first data signal line, a second compensation capacitor connected to the second data signal line, and a third compensation capacitor connected to the third data signal line, a capacitance value of the third compensation capacitor is greater than a capacitance value of the first compensation capacitor, which that of the second compensation capacitor.

Abstract: A display substrate, a working method thereof, and a display device. The display substrate includes K pixel rows and K is a positive integer greater than 1; at least one pixel row includes an initial signal line, a scan signal line, and a plurality of sub-pixels disposed sequentially along an extension direction of the initial signal line and the scan signal line; the initial signal line includes a third initial signal line, the scan signal line includes a second scan signal line, at least one sub-pixel includes a pixel drive circuit, the pixel drive circuit at least includes a third transistor as a drive transistor and an eighth transistor as an initialization transistor; in at least a pixel row, the eighth transistor is connected with the third initial signal line, the second scan signal line, and a second electrode of the drive transistor.

Abstract: Disclosed is the use of Bifidobacterium lactis BL-99 in the protection of cartilage. Provided in the present invention is the use of Bifidobacterium lactis in the preparation of a composition for protecting cartilage, wherein the Bifidobacterium lactis is Bifidobacterium lactis with the deposit number of CGMCC No. 15650. The Bifidobacterium lactis can promote the development of cartilage, increase cartilage density, protect cartilage from damage, promote cartilage repair and/or ameliorate cartilage damage, and is beneficial to cartilage health.

Abstract: Exemplary processing methods may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature. The methods may include forming plasma effluents of the silicon-containing precursor. The methods may include depositing a silicon-containing material on the substrate. The methods may include providing an oxygen-containing precursor to the processing region, forming plasma effluents of the oxygen-containing precursor, and contacting the silicon-containing material with the plasma effluents of the oxygen-containing precursor to form a silicon-and-oxygen-containing material.

Abstract: An array substrate is provided. The array substrate includes K number of reset signal lines respectively configured to provide reset signals to reset transistors in K columns pixel driving circuits of the array substrate. The K number of reset signal lines includes a plurality of third reset signal lines in (2k?1)-th columns of K columns, K and k being positive integers, 1?k?(K/2), and a plurality of fourth reset signal lines in (2k)-th columns of the K columns. A respective third reset signal line and a respective fourth reset signal line have different line patterns.

Abstract: Disclosed is a display substrate, including a base substrate (100), a circuit structure layer disposed on the base substrate (100), and a light emitting structure layer. The circuit structure layer includes a plurality of pixel circuits located in a first display region (A1), at least one first trace 231 extending along a first direction (D1), at least one second trace 232 extending along a second direction (D2), and at least one third trace located in a peripheral region (BB). The at least one first trace (231) is electrically connected with the at least one second trace (232) and the at least one third trace is electrically connected with at least one of following; the at least one first trace (231) and the at least one second trace (232).

Abstract: An array substrate is provided. The array substrate includes a plurality of first type data lines and a plurality of second type data lines. A respective one of the plurality of first type data lines crosses over subpixel apertures of multiple subpixels of a first color, and does not crosses over subpixel apertures of any subpixel of a second color and does not crosses over subpixel apertures of any subpixel of a third color, the first color, the second color, and the third color being different colors. A respective one of the plurality of second type data line does not cross over any subpixel aperture. A respective subpixel aperture of a subpixel of the first color includes a first region and a second region. A ratio of a first area of the first region to a second area of the second region is in a range of 2:8 to 8:2.

Abstract: A display substrate and a display device are provided. The display substrate includes a first power signal line and a pixel defining layer. The first power signal line includes first power signal sub-lines extending along a first direction and second power signal sub-lines extending along a second direction. The pixel defining layer includes a plurality of openings to define effective light-emitting regions of a plurality of sub-pixels, the plurality of sub-pixels include a sub-pixel pair including two sub-pixels arranged along the second direction, and the sub-pixel pair includes two effective light-emitting sub-regions with an interval therebetween. In a plan view, the first power signal sub-line passes through the interval between the two effective light-emitting sub-regions, at least one second power signal sub-line includes a fracture, and the two effective light-emitting sub-regions are located at the fracture.

Abstract: A display panel includes a base substrate, a circuit structure layer, a light emitting structure layer, and multiple conductive layers. The conductive layer is located between the circuit structure layer and the light emitting structure layer and includes multiple conductive lines. At least one second pixel drive circuit of the multiple second pixel drive circuits is electrically connected to at least one second light emitting device of the second light emitting devices through a conductive line, and the at least one second pixel drive circuit is configured to drive the at least one second light emitting device to emit light. There is an overlap between orthographic projections of the portions of conductive lines of at least two of the multiple conductive layers extending in the first direction on the base substrate.

Abstract: A display substrate and a display device are provided. The display substrate includes a first power signal line and a pixel defining layer. The first power signal line includes first power signal sub-lines extending along a first direction and second power signal sub-lines extending along a second direction. The pixel defining layer includes a plurality of openings to define effective light-emitting regions of a plurality of sub-pixels, the plurality of sub-pixels include a sub-pixel pair including two sub-pixels arranged along the second direction, and the sub-pixel pair includes two effective light-emitting sub-regions with an interval therebetween. In a plan view, the first power signal sub-line passes through the interval between the two effective light-emitting sub-regions, at least one second power signal sub-line includes a fracture, and the two effective light-emitting sub-regions are located at the fracture.

Abstract: Disclosed are a display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a display region and a bonding region, wherein the display region includes M pixel rows arranged sequentially, at least one pixel row includes a scan signal line and a plurality of sub-pixels arranged sequentially along an extension direction of the scan signal line, at least one sub-pixel includes a pixel drive circuit connected with the scan signal line, the pixel drive circuit at least includes a storage capacitor and a first transistor as a first initialization transistor, and the scan signal line at least includes a second scan signal line that controls the first transistor to be turned on or off, and in the at least one pixel row, the second scan signal line is arranged on a side of the storage capacitor close to a display region boundary.

Abstract: A display substrate and a display apparatus are provided, wherein the display substrate includes: a base substrate and a drive structure layer provided on the base substrate, the drive structure layer includes pixel circuits arranged in an array, the pixel circuits arranged in an array includes a plurality of power supply lines; the pixel circuit further includes a capacitor, the capacitor includes a first electrode plate and a second electrode plate; the plurality of power supply lines include a plurality of first power connection lines disposed in a first conductive layer and a plurality of second power connection lines disposed in a second conductive layer, the second conductive layer is located on a side of the first conductive layer away from the base substrate, the first power connection line and the second power connection line extend in a first direction.

Abstract: An array substrate includes a plurality of pixel driving circuits, and each pixel driving circuit at least includes a compensation transistor. The array substrate includes a substrate, an active layer, a first gate layer and a second gate layer. The active layer includes an active layer pattern of the compensation transistor, which includes two channel areas and a conductive area therebetween. The first gate layer includes a first gate signal line, and an orthographic projection of the first gate signal line on the substrate is overlapped with orthographic projections of the two channel areas on the substrate. The second gate layer includes a voltage stabilization pattern, which is configured to receive a power supply voltage signal, and an orthographic projection of the voltage stabilization pattern on the substrate is overlapped with an orthographic projection of the conductive area on the substrate.