Abstract: Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter, having a chain of five DFFs.

Abstract: A voltage-controlled oscillator circuit. A pair of inductors are coupled to a first power source. A pair of capacitors respectively coupled between a variable resistor and the pair of inductors in serial. A pair of first switches respectively coupled between the pair of capacitors and a second power source. The first switch of the pair has a first control gate coupled to a connection point of the other first switch and the corresponding capacitor.

Abstract: Methods and systems of the present invention may be used to recognize digital image data arranged in rows and columns. Exemplary embodiments may include a feature extractor for extracting feature information from data representing the rows and columns of the digital image data, a feature compressor for compressing the extracted feature information, and a neural network for classifying the digital image data from the compressed, extracted feature information.

Abstract: A handwriting recognition device using fuzzy logic and cellular neural network for unconstrained handwritten numeral classification is provided. The current mode VLSI classifier has a I/O circuit for inputting and outputting a plurality of membership functions. An extraction unit comprising a CCD extractor with a CNN structure and a compression unit receives a to-be-recognized character having a plurality of input features for generating a plurality of features values after compression. A membership function generator stores the plurality of membership functions and receives the plurality of features values to generate a plurality of current-type membership degrees. A plurality of switched-current integrators receives the plurality of current-type membership degrees for generating a plurality of synthesis membership degrees.

Abstract: A neural fuzzy data classifier for handwritten character classification is provided. The classifier has an I/O circuit for inputting and outputting a plurality of membership functions. An input buffer receives a to-be-recognized character having a plurality of input features for generating a plurality of features values. A main computation unit comprising a computation array and a local thresholds block store the plurality of membership functions and receives the plurality of features values to generate a plurality of current-type weights. A difference circuit block compares the current output from the computation array and local thresholds lock. A plurality of switched-current integrators receives the plurality of current-type weights for generating a plurality of synthesis weights.

Abstract: Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter, having a chain of five DFFs.

Abstract: An analog circuit for calculating square and reciprocal of a current is provided. It is an analog integrated circuit and can make the input and output signals become currents in the current field of the same type of analog integrated circuit. The output current can be the square or reciprocal of the input current. The square and reciprocal functions can be implemented by using three identical BJTs. Those three BJTs are independent and the bases and collectors of the BJTs are coupled to ground. Hence, the circuit can be implemented by the standard CMOS and can be applied to the other complicated system. In addition, the operational amplifier and the capacitor in the circuit are required to stabilize this circuit. This circuit has a simple structure.

Abstract: A low noise amplifier (LNA) is provided for a first block of a wireless receiver in a wireless communication system using CMOS technology. The LNA includes a first cascode amplifying module and a second cascode amplifying module, where an output signal of the first cascode amplifying module is fed to the second cascode amplifying module in order to cancel third-order intermodulation frequencies (IM3), such that input-referred third-order intercept point (IIP3) is increased and thus linearity of the LNA is improved.

Abstract: A flipflop. In the flipflop, a differential pair is coupled to two input signals inverse to each other. A first latch unit is connected to the differential pair in parallel, and includes a first node and a second node coupled to generate complementary latch signals according to the first and second data signals. A signal amplification circuit is coupled to the differential pair and the first latch unit to generate complementary amplified signals according to the complementary latch signals. A second latch unit is coupled to the signal amplifier circuit to generate complementary static output signals according to the complementary amplified signals and to maintain the complementary static output signals.

Abstract: A down-converter and a testing device for the down-converter are provided. The down-converter implements a Class-AB single-end input, differential output double balanced mixer structure. By introducing an on-chip bias loop, it significantly improves the symmetry and linearity of the mixer. The down-converter on-chip implements an input impedance match circuit and an open-drain output stage. By optimizing the circuit structure and each device, it achieves the objectives of a high conversion gain, high linearity, and low noise coefficient.

Abstract: A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the current signals. Each of the first and second I-V converters is also coupled to a current generator which generates a current that linearly changes with time. For each of the first and second I-V converters, when a polarity of the input current thereof changes, an output changes between a high voltage level and a low voltage level. A logic circuit is coupled to the first and each second I-V converter to obtain a pulse signal that has a pulse width linearly proportional to the current level of the respective current signal.

Abstract: A voltage-controlled oscillator circuit. A pair of inductors are coupled to a first power source. A pair of capacitors respectively coupled between a variable resistor and the pair of inductors in serial. A pair of first switches respectively coupled between the pair of capacitors and a second power source. The first switch of the pair has a first control gate coupled to a connection point of the other first switch and the corresponding capacitor.

Abstract: A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

Abstract: An analog circuit for calculating square and reciprocal of a current is provided. It is an analog integrated circuit and can make the input and output signals become currents in the current field of the same type of analog integrated circuit. The output current can be the square or reciprocal of the input current. The square and reciprocal functions can be implemented by using three identical BJTs. Those three BJTs are independent and the bases and collectors of the BJTs are coupled to ground. Hence, the circuit can be implemented by the standard CMOS and can be applied to the other complicated system. In addition, the operational amplifier and the capacitor in the circuit are required to stabilize this circuit. This circuit has a simple structure.

Abstract: A circuit for extracting a connected component feature from an input image includes an input stage, a counting stage, a bit-preparing stage, and a bit-output stage. The input stage receives a bit pattern and detects a connected component in the bit pattern. The counting stage counts the number of connected components detected in the input stage and generates a current representing that number. The bit-preparing stage generates more than one current as a basis for information including more than one bit, based on the current generated in the counting stage, so that the information uniquely represents the number of connected components. The bit-output stage converts the currents generated in the bit-preparing stage into a digital output corresponding to the information.

Abstract: A low noise amplifier (LNA) is provided for a first block of a wireless receiver in a wireless communication system using CMOS technology. The LNA includes a first cascode amplifying module and a second cascode amplifying module, where an output signal of the first cascode amplifying module is fed to the second cascode amplifying module in order to cancel third-order intermodulation frequencies (IM3), such that input-referred third-order intercept point (IIP3) is increased and thus linearity of the LNA is improved.

Abstract: A down-converter and a testing device for the down-converter are provided. The down-converter implements a Class-AB single-end input, differential output double balanced mixer structure. By introducing an on-chip bias loop, it significantly improves the symmetry and linearity of the mixer. The down-converter on-chip implements an input impedance match circuit and an open-drain output stage. By optimizing the circuit structure and each device, it achieves the objectives of a high conversion gain, high linearity, and low noise coefficient.

Abstract: A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

Abstract: A flipflop. In the flipflop, a differential pair is coupled to two input signals inverse to each other. A first latch unit is connected to the differential pair in parallel, and includes a first node and a second node coupled to generate complementary latch signals according to the first and second data signals. A signal amplification circuit is coupled to the differential pair and the first latch unit to generate complementary amplified signals according to the complementary latch signals. A second latch unit is coupled to the signal amplifier circuit to generate complementary static output signals according to the complementary amplified signals and to maintain the complementary static output signals.

Abstract: A current-mode synapse multiplier circuit multiplies each of a plurality of pulse signals with each of a corresponding plurality of weight signals. The synapse multiplier includes a plurality of first switches each coupled to a corresponding pulse signal and the corresponding weight signal. An integral circuit is coupled to the first switches to receive the weight signals that pass through the first switches and integrates the sum of the weight signals that pass through the first switches over a period of time. A voltage-to-current (V-I) converter is coupled to the integral circuit to convert the integral of the sum of the weight signals that pass through the first switches into a current signal, wherein the current signal represents the sum of the multiplication products of each pulse signal and the corresponding weight signal. An external reset signal is coupled to the synapse multiplier through a second switch to reset the synapse multiplier.