Abstract: A neural network system includes a feedforward network comprising at least one neuron circuit for producing an activation function and a first derivative of the activation function and a weight updating circuit for producing updated weights to the feedforward network. The system also includes an error back-propagation network for receiving the first derivative of the activation function and to provide weight change data information to the weight updating circuit.

Abstract: A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the current signals. Each of the first and second I-V converters is also coupled to a current generator which generates a current that linearly changes with time. For each of the first and second I-V converters, when a polarity of the input current thereof changes, an output changes between a high voltage level and a low voltage level. A logic circuit is coupled to the first and each second I-V converter to obtain a pulse signal that has a pulse width linearly proportional to the current level of the respective current signal.

Abstract: A current-mode synapse multiplier circuit multiplies each of a plurality of pulse signals with each of a corresponding plurality of weight signals. The synapse multiplier includes a plurality of first switches each coupled to a corresponding pulse signal and the corresponding weight signal. An integral circuit is coupled to the first switches to receive the weight signals that pass through the first switches and integrates the sum of the weight signals that pass through the first switches over a period of time. A voltage-to-current (V-I) converter is coupled to the integral circuit to convert the integral of the sum of the weight signals that pass through the first switches into a current signal, wherein the current signal represents the sum of the multiplication products of each pulse signal and the corresponding weight signal. An external reset signal is coupled to the synapse multiplier through a second switch to reset the synapse multiplier.

Abstract: A neuron circuit generates a sigmoid transfer function and its derivative. The neuron circuit comprises an I-V converter that converts a current input signal into a voltage signal, a first output circuit having a first differential amplifier with a first current mirror as an active load, and a second output circuit having a second differential amplifier with a second current mirror as an active load, both the first and second output circuit being coupled to the voltage signal. While an output of one of the first and second output circuits is a sigmoid function of the current input, a difference between the two outputs of the two output circuits is a derivative of the sigmoid function.

Abstract: A pattern recognition device for processing an array containing image data includes a first feature matching device, a first data compressor, and a second feature matching device. The first feature matching device matches the image data with a first feature module to generate feature information. The first feature module comprises a first set of categorizing features and the feature information identifies at least one matching categorizing feature. The first data compressor compresses the feature information to generate a feature chart for the array. The second feature matching device receives feature data created based on the feature chart and matches the feature data with a second feature module to generate a matching result. The second feature module comprises a second set of features that are provided based on the feature data.

Abstract: A current sorter has an input section, a comparing section, and a control section. The input section includes a first input unit and a second input unit and generate a first output signal that is indicative of the first input signal and a second output signal that is indicative of a level of the second input signal. The comparing section is coupled with the input section and compares the first output signal and the second output signal to responsively generate a result. The comparing section includes a first comparing unit and a second comparing unit. The control section is coupled with the input section and the comparing section. Furthermore, the control section activates, when receiving an initial load signal, the first input unit, the second input unit, the first comparing unit, and the second comparing unit.

Abstract: A current sorter has an input section, a comparing section, and a control section. The input section includes a first input unit and a second input unit and generate a first output signal that is indicative of the first input signal and a second output signal that is indicative of a level of the second input signal. The comparing section is coupled with the input section and compares the first output signal and the second output signal to responsively generate a result. The comparing section includes a first comparing unit and a second comparing unit. The control section is coupled with the input section and the comparing section. Furthermore, the control section activates, when receiving an initial load signal, the first input unit, the second input unit, the first comparing unit, and the second comparing unit.

Abstract: A pulse width modulation (PWM) neuron circuit. The neuron circuit includes an input control circuit, a charge/discharge circuit and an output control circuit. The input control circuit is coupled to an input voltage source and an operation voltage source. The charge/discharge circuit is coupled to the current mirror circuit. The output control circuit is being coupled to the charge/discharge circuit and the input control circuit. The input control circuit is activated and controlled by the output control circuit and a first current is generated from the input control circuit in accordance with the input voltage source and the operation voltage source. The charge/discharge circuit is charged to a predetermined voltage level in accordance with the first current from the input control circuit. The predetermined voltage level is sufficient enough to make an output of the output control circuit being changed with logic status of the output.

Abstract: A voltage-mode pulse width modulation (PWM) VLSI implementation of neural networks, comprising: a voltage-pulse converter for converting an input voltage into a neuron-state pulse; a synapse multiplier, including a multiplier cell for multiplying the neuron-state pulse by an input weight voltage and an integral and summation cell for integrating and summing up the multiplied output and producing a first output voltage; and a sigmoid circuit for converting the first output voltage into a second output voltage with the non-linear activation function of neuron.

Abstract: A expandable neural network with on-chip back propagation learning is provided in the present invention. The expandable neural network comprises at least one neuron array containing a plurality of neurons, at least one synapse array containing a plurality of synapses, and an error generator array containing a plurality of error generator. An improved Gilbert multiplier is provided in each synapse where the output is a single-ended current. The synapse array receives a voltage input and generates a summed current output and a summed neuron error. The summed current output is sent to the input of the neuron array where the input current is transformed into a plurality of voltage output. These voltage output are sent to the error generator array for generating a weight error according to a control signal and a port signal.

Abstract: Methods and systems of the present invention may be used to recognize digital image data arranged in rows and columns. Exemplary embodiments may include a feature extractor for extracting feature information from data representing the rows and columns of the digital image data, a feature compressor for compressing the extracted feature information, and a neural network for classifying the digital image data from the compressed, extracted feature information.

Abstract: A pulse width modulation (PWM) neuron circuit. The neuron circuit includes an input control circuit, a charge/discharge circuit and an output control circuit. The input control circuit is coupled to an input voltage source and an operation voltage source. The charge/discharge circuit is coupled to the current mirror circuit. The output control circuit is being coupled to the charge/discharge circuit and the input control circuit. The input control circuit is activated and controlled by the output control circuit and a first current is generated from the input control circuit in accordance with the input voltage source and the operation voltage source. The charge/discharge circuit is charged to a predetermined voltage level in accordance with the first current from the input control circuit. The predetermined voltage level is sufficient enough to make an output of the output control circuit being changed with logic status of the output.

Abstract: A handwriting recognition device using fuzzy logic and cellular neural network for unconstrained handwritten numeral classification is provided. The current mode VLSI classifier has a I/O circuit for inputting and outputting a plurality of membership functions. An extraction unit comprising a CCD extractor with a CNN structure and a compression unit receives a to-be-recognized character having a plurality of input features for generating a plurality of features values after compression. A membership function generator stores the plurality of membership functions and receives the plurality of features values to generate a plurality of current-type membership degrees. A plurality of switched-current integrators receives the plurality of current-type membership degrees for generating a plurality of synthesis membership degrees.

Abstract: A circuit for extracting a connected component feature from an input image includes an input stage, a counting stage, a bit-preparing stage, and a bit-output stage. The input stage receives a bit pattern and detects a connected component in the bit pattern. The counting stage counts the number of connected components detected in the input stage and generates a current representing that number. The bit-preparing stage generates more than one current as a basis for information including more than one bit, based on the current generated in the counting stage, so that the information uniquely represents the number of connected components. The bit-output stage converts the currents generated in the bit-preparing stage into a digital output corresponding to the information.

Abstract: The current controlled sigmoid neural circuit is used for approximating sigmoid function and is simple constructed, current controlled and gain adjustable circuit with highly precision. The present invention comprises a voltage generator for converting a current input into a voltage, a pair of differential amplifier for generating sigmoid-like function and few pairs of current mirrors for providing reference currents. By using adjustable reference current and gain factor, the circuit has a large range and high noise immunity and can approximate sigmoid function with insignificant error.

Abstract: A neural network includes a programmable template matching network and a winner take all network. The programmable template matching network can be programmed with different templates. The WTA network has an output which can be reconfigured and the scale of the WTA network can expanded.

Abstract: A neural network includes a neuron, an error determination unit, and a weight update unit. The weight update unit includes an analog accumulator. The analog accumulator requires a minimal number of multipliers.

Abstract: A neural fuzzy data classifier for handwritten character classification is provided. The classifier has an I/O circuit for inputting and outputting a plurality of membership functions. An input buffer receives a to-be-recognized character having a plurality of input features for generating a plurality of features values. A main computation unit comprising a computation array and a local thresholds block store the plurality of membership functions and receives the plurality of features values to generate a plurality of current-type weights. A difference circuit block compares the current output from the computation array and local thresholds lock. A plurality of switched-current integrators receives the plurality of current-type weights for generating a plurality of synthesis weights.

Abstract: A novel 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phases-selection block is provided in the present invention. The master latch and slave latch comprise a pair of input terminals, a pair of control terminals, and a pair of output terminals. The master latch further comprises two pairs of complementary cross-couple transistors for amplifying the output of the master latch for entering the phase-selection block. The phase-selection block has a pair of input terminals, a clock signal input terminal, and an output terminal generating an output signal adjusted by a division ratio according to the clock signal. The division ratio is either 1/2 or 1/3 and the divider functions as a 2/3 divider.

Abstract: A neural network system includes a feedforward network comprising at least one neuron circuit for producing an activation function and a first derivative of the activation function and a weight updating circuit for producing updated weights to the feedforward network. The system also includes an error back-propagation network for receiving the first derivative of the activation function and to provide weight change data information to the weight updating circuit.