Abstract: The invention provides a new hybrid 4-in-1 power controller chip for a PC mainboard which integrates a synchronous buck switching regulator to supply the CPU core voltage, a standard buck switching regulator for I/O circuits, a linear controller for the GTL bus, and a linear regulator with built-in pass transistor for a clock generator. On this basis, a hybrid power system for a PC mainboard is constructed. As compared with the conventional separate power systems on a PC mainboard, the hybrid power system of the present invention can save board area and reduce cost. Test results show this system has high precision and its synchronous switching regulator meets the specifications of Intel's VRM8.4 design guidelines for Pentium III CPUs.

Abstract: The invention provides a new hybrid 4-in-1 power controller chip for a PC mainboard which integrates a synchronous buck switching regulator to supply the CPU core voltage, a standard buck switching regulator for I/O circuits, a linear controller for the GTL bus, and a linear regulator with built-in pass transistor for a clock generator. On this basis, a hybrid power system for a PC mainboard is constructed.

Abstract: A voltage-mode pulse width modulation (PWM) VLSI implementation of neural networks, comprising: a voltage-pulse converter for converting an input voltage into a neuron-state pulse; a synapse multiplier, including a multiplier cell for multiplying the neuron-state pulse by an input weight voltage and an integral and summation cell for integrating and summing up the multiplied output and producing a first output voltage; and a sigmoid circuit for converting the first output voltage into a second output voltage with the non-linear activation function of neuron.

Abstract: A hybrid 4-in-1 power controller chip for a PC mainboard which integrates a synchronous buck switching regulator to supply the CPU core voltage, a standard buck switching regulator for I/O circuits, a linear controller for the GTL bus, and a linear regulator with built-in pass transistor for a clock generator. Therefore, a hybrid power system for a PC mainboard is constructed.

Abstract: A k-WTA circuit for selecting inputs which have a maximum-magnitude and outputting the results. k-WTA is very useful in pattern classification such as k-nearest neighbor classifier, Hamming neural classifier and some cascaded classification systems, since one classifier can not achieve very high performance, however, if a small set of candidates can be provided, for example k(k<<N), then a simple classifier with small complementary feature sets can be cascaded to realize multi-stage classification. A k-WTA network is necessary to implement this function. The circuit as disclosed in the invention provides a design for a circuit in which the number of inputs with maximum magnitudes at any one time can be chosen. The circuit can have a plurality of inputs each of which has a corresponding output. In one embodiment of the invention external inputs can select the number of maximum-magnitudes inputs to be selected through the use of a current positive feedback loop.

Abstract: This invention relates to an artificial neural network (ANN), particularly to a neuron circuit and its activation function including the derivative. The neuron circuit capable of generating an adjustable sigmoid-like function and a good approximation of its derivative, comprises: a current generator for generating a current; a current-controlled transistor for changing an output voltage according to the current from the current generator; and at least one differential pair of transistors for generating the adjustable sigmoid-like function output and the good approximation of its derivative by the changed output voltage.

Abstract: A synchronous pulse width modulation (PWM) switching regulator that is suitable for high-performance CPUs. A DAC converts a plurality of inputted digital signal into analog signal that indicates the desired voltage. A circuit creates the necessary PWM signal to control a pair of drivers and their associated switches to convert a first inputted voltage to a second desired voltage. A soft-start circuit ensures that the startup voltage does not overshoot an expected level. Over-current and over-voltage protection circuits ensure that the circuit will not damage any circuits that power is supplied to.

Abstract: This invention relates to an artificial neural network (ANN), particularly to a neuron circuit and its activation function including the derivative. The neuron circuit capable of generating an adjustable sigmoid-like function and a good approximation of its derivative, comprises: a current generator for generating a current; a current-controlled transistor for changing an output voltage according to the current from the current generator; and at least one differential pair of transistors for generating the adjustable sigmoid-like function output and the good approximation of its derivative by the changed output voltage.

Abstract: The invention provides a new hybrid 4-in-1 power controller chip for a PC mainboard which integrates a synchronous buck switching regulator to supply the CPU core voltage, a standard buck switching regulator for I/O circuits, a linear controller for the GTL bus, and a linear regulator with built-in pass transistor for a clock generator. On this basis, a hybrid power system for a PC mainboard is constructed.

Abstract: A winner-take-all (WTA) circuit apparatus for comparing two current inputs from a WTA circuit to a threshold current to create a reject signal, to assist in the decision criteria of a winner-take-all network. The circuit compares the two input currents from the WTA circuit by using NMOS transistors which perform electrical mathematical functions by manipulating the currents. The end result is that the difference of the two currents is compared with a reference current and a voltage level is outputted. The reference current is adjustable, and the invention also provides a WTA circuit with weighted inputs, and the ability to select between a 1-WTA, and a 2-WTA configuration. The invention therefore solves the problems of prior art by being capable of properly selecting current levels or rejecting current levels which are too close in value, with a voltage reject signal.

Abstract: A Hamming neural network circuit which can be programmed and expanded is disclosed. The Hamming neural network includes an I/O circuit for inputting and outputting a plurality of standard patterns. A bi-directional transmission gate array is connected to the I/O circuit and controlled by a programming signal for transmitting the standard patterns. A plurality of standard pattern memory units is connected to the bi-directional transmission gate array for storing the plurality of standard patterns respectively. An address decoder is connected to the plurality of standard pattern memory units for addressing one of the plurality of standard pattern memory units. A plurality of pattern matching calculation circuit units are respectively connected to the plurality of standard pattern memory units for generating a plurality of matching rates between a to-be-recognized pattern and the plurality of standard patterns.

Abstract: A CMOS current comparator featuring shortened response delay times lower power consumption, smaller area and enhanced process robustness. The current comparator is comprised of a CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. The CMOS complementary amplifier receives an input current from an input node which generates an output voltage at a corresponding output node. The CMOS complementary amplifier is comprised of an N-type metal oxide semiconductor field effect transistor (NMOS) and a P-type metal oxide semiconductor field effect transistor (PMOS) connected in series. Control gates on both the NMOS and PMOS are connected to form the input node. NMOS and PMOS drain electrodes are also coupled to the output node. The CMOS complementary amplifier further has a resistive feedback circuit which is connected between the input and output nodes.

Abstract: A fuzzy processor which can be programmed and expanded is disclosed. The fuzzy processor has a membership function I/O circuit for inputting and outputting a plurality of membership functions respectively corresponding to each one of a plurality of features of each one of a plurality of standard patterns. A feature decoder receives a to-be-recognized pattern having a plurality of input features for generating a plurality of feature values. A membership function generator stores the plurality of membership functions and receives the plurality of feature values to generate a plurality of current-type membership degrees for the plurality of input features corresponding to the plurality of standard patterns respectively. A plurality of accumulators receive the plurality of current-type membership degrees respectively for generating a plurality of synthesis membership degrees.

Abstract: A signal sorter for magnitude sorting among a number of signals is disclosed that allows for magnitude sorting of a number of signals in an ascending or descending ordered manner governed by the clock controlling signals. The sorter can generate sorted outputs fast enough for real-time applications and has a circuit structure suitable for implementation as integrated circuit devices. The sorter has a signal input section, maximum-deriving section, a feedback control and voltage output section and a sorted output section. All four sections are controlled by a set of timing clock input signals to manipulate the signal magnitude sorting.

Abstract: A current-type fuzzy processor is disclosed. The fuzzy processor comprises a characteristic decoder for decoding a to-be-identified pattern, a plurality of membership function generators for generating a plurality of membership degrees for the to-be-identified pattern, a weighting decoder for generating a weighting value, a plurality of weighting adjustment circuits for performing weighting operations on the plurality of membership degrees according to the weighting value to generate a plurality of weighted membership degrees, a plurality of accumulators for performing accumulation operations on the plurality of weighted membership degrees to generate a plurality of synthesis membership degrees, a WTA circuit for outputting the plurality of synthesis membership degrees in an order of magnitude; and a timing and control logic for generating timing and control signals for the fuzzy processor.

Abstract: A current sorter for sorting a plurality of currents is disclosed. The current sorter comprises an input circuit unit for receiving a plurality of input currents to be sorted, a winner-take-all (WTA) circuit unit for finding the maximum current, a feedback control and voltage output circuit unit for generating feedback control signals and output voltages indicating the maximum current, and an output circuit unit for outputting sorted currents. A plurality of input currents are simultaneously input to the input circuit unit and the sorted results are output in a time-shared manner on the output circuit unit.

Abstract: A switched-current fuzzy processor for pattern recognition is provided, which is specifically designed to operate in current mode for high performance. The switched-current fuzzy processor includes means for decoding a feature input into a set of binary feature signals; an array of MFGs, coupled to the decoding means, for obtaining a set of current outputs whose magnitudes are proportional to the values of the feature signals respectively; weight-adjusting means, coupled to the MFG array, for applying a predetermined weight factor in binary form to the output currents from the MFG array; summing means, coupled to the weight-adjusting means, for summing up each set of currents from each column of the MFGs in the MFG array to thereby obtain a total value for the currents therefrom; and a maximum-value determination circuit, coupled to the summing means, capable of obtaining the one of the currents with the maximum magnitude from the summing means.

Abstract: A switched capacitor sorter based on magnitude includes a plurality of input units, a winner-take-all (WTA) circuit for finding a maximum voltage level, and an output unit. A plurality of input voltages are simultaneously input to the respective input units, and the sorted results are output in a time-shared manner.

Abstract: Disclosed is a two-layer switched-current type of a Hamming neural network system. This Hamming network system includes a matching rate computation circuit for modules on a first layer used to compute a matching rate between a to-be-identified pattern and each one of a plurality of standard patterns, a matching rate comparison circuit on a second layer for ranking an order of the matching rates including a switched-current type order-ranking circuit for receiving switched-current signals, finding a maximum value and outputting a time-division order-ranking output and an identification-rejection judgment circuit for performing an absolute and a relative judgment, and a pulse-generating circuit for generating sequential clock pulses, in which the circuit construction of the Hamming network is simple and flexible due to a modular design with extendible circuit dimensions, and a high precision, improved performance and enhanced reliability of the network system is achieved.

Abstract: A current-mode Hamming neural network is provided with N binary inputs, and has a template matching calculation subnet and a winner-take-all subnet. The template matching calculation subnet includes M first neurons in which M exemplar templates are stored respectively. Each first neuron is consisted of current mirrors connected to and controlled by the N binary inputs respectively, to generate a template matching current signal which is substantially proportional to the number of matched bits between the N binary inputs and the corresponding stored exemplar template. The winner-take-all subnet includes M second neurons, each including M transistors with their gate electrodes connected together to form a template competition node, their source electrodes connected to ground, and their drain electrodes connected to the template competition nodes respectively.