Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.

Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer.

Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.

Abstract: A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.

Abstract: Provided is an array substrate. The array substrate includes: a base substrate, and a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines disposed on the base substrate. The data lines have a plurality of first extending parts and a plurality of second extending parts which are in an alternating arrangement. When the array substrate is used to prepare a liquid crystal display panel and the liquid crystal display panel is displaying, in each column of the sub-pixels, the voltage polarities of the two adjacent sub-pixels which respectively belong to two adjacent first pixel regions are opposite.

Abstract: A nylon tube automatic thermoforming apparatus includes a main body, a conveying assembly, a heating assembly and a tube bending assembly. The heating assembly includes an oven communicated with the conveying assembly and an electrically heated cylinder arranged between the oven and the tube bending assembly. A heating coil is arranged in the electrically heated cylinder. A nylon tube is conveyed from the conveying assembly and enters the tube bending assembly via the oven and the heating coil. The electrically heated cylinder and the tube bending assembly are arranged outside the main body. A nylon tube shaping process includes the steps of drawing, heating inside a main body, heating outside the main body, bending, staying, feeding, angle adjusting, repeating the above steps until the length and the curvature of the nylon tube meet the requirements, and cutting off.

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

Abstract: The present invention discloses a disaster prevention, early warning and production decision support method and system for a power distribution network, and relates to the technical field of the power distribution network. Various data is fused, a maximum wind load, a lightning trip-out rate, a maximum carrying capacity at a highest operation temperature and an average failure frequency and time under an environmental factor are calculated, and a power outage risk is evaluated and classified; and after an emergency, a power grid topology is analyzed, and a device outage probability is calculated to obtain a load power outage probability and risk and provide disaster early warning, monitoring and rush repair decision support.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.

Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

Abstract: A transmission mechanism of a micro crawling robot and the micro crawling robot. The transmission mechanism is a parallel mechanism with three branch chains and two degrees of freedom, and comprises: a fixed platform; a moving platform; a constraint limb comprising a first rotating joint S11 and a second rotating joint S12, which generate the functions of restraining the lifting motion and the twisting motion of the moving platform, respectively; a first actuation limb comprising third to seventh rotating joints S21-S25, wherein the third rotating joint S21 is a actuation joint and the rest are transmission rotating joints; and a second actuation limb comprising eighth to twelfth rotating joints S31-S35, wherein the eighth rotating joint S31 is a actuation joint, and the rest are the transmission rotating joints.

Abstract: The present invention discloses a capsule endoscope, which comprises an enclosure, and an imaging unit, a data processing unit and an antenna unit arranged in the enclosure. The enclosure comprises a cylindrical middle enclosure and two hemispherical covers connected to both ends of the middle enclosure, and the antenna unit is arranged close to the inner surface of the middle enclosure. The antenna unit is arranged close to the inner surface of the middle enclosure. Such arrangement can save internal space and improve the space utilization, and also, the arrangement of the antenna unit does not affect the layout of the imaging unit.

Abstract: A memory cell includes a transistor including a memory film extending along a word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; a source line extending along the memory film, wherein the memory film is between the source line and the word line; a first contact layer on the source line, wherein the first contact layer contacts the channel layer and the memory film; a bit line extending along the memory film, wherein the memory film is between the bit line and the word line; a second contact layer on the bit line, wherein the second contact layer contacts the channel layer and the memory film; and an isolation region between the source line and the bit line.

Abstract: A separator includes a porous substrate and a porous coating. The porous coating is disposed on at least one surface of the porous substrate. The porous coating includes inorganic particles and a binder. The binder includes a first binder. The first binder includes a metal element. The separator of this application is excellent in thermal safety stability and mechanical stability, mainly manifested in that, when a rupture hole is generated on the separator by thermally puncturing the separator by using a round needle with a diameter of R heated to 500° C., a maximum value of a distance between any two points on an edge of the rupture hole is r in a case that the two points are connected to form a line and the distance between the two points is calculated, satisfying: 400 ?m?R?1000 ?m, and 0.9?r/R?5.

Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

Abstract: Gates having air gaps therein, and methods of fabrication thereof, are disclosed herein. An exemplary gate includes a gate electrode and a gate dielectric. A first air gap is between and/or separates a first sidewall of the gate electrode from the gate dielectric, and a second air gap is between and/or separates a second sidewall of the gate electrode from the gate dielectric. A dielectric cap may be disposed over the gate electrode, and the dielectric cap may wrap a top of the gate electrode. The dielectric cap may fill a top portion of the first air gap and a top portion of the second air gap. The gate may be disposed between a first epitaxial source/drain and a second epitaxial source/drain, and a width of the gate is about the same as a distance between the first epitaxial source/drain and the second epitaxial source/drain.

Abstract: A separator includes a porous substrate and a porous coating disposed on at least one surface of the porous substrate, where the porous coating includes a polymer and a thickness covariance value of the separator is 0.01 to 0.02. The separator provided has good thickness consistency, which is conducive to improving the packaging performance of the electrochemical device, and the resulting electronic device has a longer service life and good usage performance.

Abstract: A flying capacitor converter, a voltage converter and an energy storage system are provided. The flying capacitor converter includes a high-voltage side, a low-voltage side, a power switch unit, a current switch unit and a current detection unit. The high-voltage side is electrically connected with a first power source. The low-voltage side is electrically connected with a second power source. The power switch unit is electrically connected between the high-voltage side and the low-voltage side and includes three terminals and four power switches. The current switch unit is electrically connected with the high-voltage side, the low-voltage side and/or a common node. The current detection unit is electrically connected between a third terminal of the power switch unit and the common node. If the current detected by the current detection unit indicates that a short-circuit condition occurs, the power switch unit is disconnected from the high-voltage side and/or the low-voltage side.