Patents by Inventor Bo Feng

Bo Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11410627
    Abstract: The embodiment of the present disclosure provides a dual gate array substrate and a display device. The dual gate array substrate includes pairs of gate lines and data lines. The pairs of gate lines and the data lines intersect perpendicularly to define multiple display units arranged in an array. The display units include two sub-pixels of a same color, and the sub-pixels of the same color on both sides of one data line are coupled to the one data line.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 9, 2022
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenjun Xiao, Shijun Wang, Wenkai Mu, Bingqing Yang, Yi Liu, Bo Feng, Xiaoxiao Chen, Yang Wang, Zhiying Bao, Haoliang Ji, Tianxin Zhao, Ji Dong, Hao Xu
  • Publication number: 20220247672
    Abstract: The present invention discloses a LAN system, method and unit supporting dynamic self-adaptive network configuration. Through the integration of self-adaptive dynamic routing protocol with various nodes of network, the source node broadcasts and sends a message containing destination node information, and the intermediate node searches the destination node information in its connection state sheet and returns to the source node or adds its node information into the message and sends to other intermediate nodes based on the searching results, the intermediate node will modify its routing list and open the routing transfer function. The source node and the destination node will configure their routing lists respectively with the gateway and corresponding network interfaces through which the network segment of other node is reached to establish a routing connection. The system can automatically configure the network, and greatly decrease its dependence on the central node, increasing stability and reliability.
    Type: Application
    Filed: January 30, 2022
    Publication date: August 4, 2022
    Inventors: Bo Wei, Song Luo, Wei Feng, Junlan Duan
  • Publication number: 20220246441
    Abstract: A method of forming a semiconductor device includes forming a dummy gate over a substrate, forming dielectric materials over a top surface and sidewalls of the dummy gate, and replacing the dummy gate with a gate structure. The dummy gate has a first width located a first distance away from the substrate, a second width located a second distance away from the substrate, and a third width located a third distance away from the substrate. The second distance is less than the first distance. The second width is less than the first width. The third distance is less than the second distance. The third width is greater than the second width.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Bo-Feng Young, Chia-Yang Liao
  • Patent number: 11402942
    Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes: a base substrate; a plurality of gate lines on the base substrate; and a touch electrode layer located on a side, away from the base substrate, of a layer where the gate lines are located. The touch electrode layer includes a plurality of touch electrodes, and the touch electrodes are provided with first hollowed-out areas at the positions of at least part of the gate lines.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: August 2, 2022
    Assignees: Beijing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Yi Liu, Shijun Wang, Wenkai Mu, Bo Feng, Xinlan Yang, Xiaoxiao Chen, Yang Wang, Zhan Wei, Tengfei Ding, Xiaofeng Yin
  • Patent number: 11404444
    Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extends through the first layer stack and the second layer stack, where the openings includes first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Han-Jong Chia
  • Patent number: 11404570
    Abstract: A method includes providing a structure having a substrate, gate stacks and source/drain (S/D) features over the substrate, S/D contacts over the S/D features, one or more dielectric layers over the gate stacks and the S/D contacts, and a via structure penetrating the one or more dielectric layers and electrically connecting to one of the gate stacks and the S/D contacts. The method further includes forming a ferroelectric (FE) stack over the structure, wherein the FE stack includes an FE layer and a top electrode layer over the FE layer, wherein the FE stack directly contacts the via structure; and patterning the FE stack, resulting in a patterned FE stack including a patterned FE feature and a patterned top electrode over the patterned FE feature.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Han-Jong Chia, Bo-Feng Young, Yu-Ming Lin
  • Publication number: 20220238647
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure includes a contact structure surrounding the first source/drain layer, wherein a first portion of the contact structure is between the first source/drain layer and the substrate.
    Type: Application
    Filed: January 28, 2021
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sai-Hooi YEONG, Bo-Feng YOUNG, Ching-Wei TSAI
  • Patent number: 11397658
    Abstract: Techniques for a service provider network to allow users to quickly and easily establish a testing environment to test various virtual machine (VM) instance types for hosting their workloads. Rather than identifying and recommending optimized VM instance types for hosting workloads of users, the techniques allow for users to initially test the VM instance types and determine how well their workloads perform on the VM instance types. Users can quickly and easily (e.g., “one-click” input) request that a testing environment be established. The optimization service can then test one or more recommended VM instance types for the users' workloads in the testing environment. The optimization service can monitor the performance of the VM instance types while they host the “test workloads,” and provide the users with performance metrics to help them decide if they would like to migrate their workloads to the recommended VM instance types.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: July 26, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Bo Pang, Qijia Chen, Leslie Johann Lamprecht, Mohit Gupta, Letian Feng, Roberto Pentz De Faria
  • Publication number: 20220231050
    Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a multi-layer stack, a plurality of memory cells, and a plurality of conductive contacts. The substrate includes an array region and a staircase region. The multi-layer stack is disposed on the substrate in the array region, wherein the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure. The plurality of memory cells are respectively disposed on sidewalls of the multi-layer stack in the array region, and arranged at least along a stacking direction of the multi-layer stack. The plurality of conductive contacts are respectively on the staircase structure. At least two conductive contacts are electrically connected to each other.
    Type: Application
    Filed: August 11, 2021
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Shih-Lien Linus Lu, Chia-En Huang, Yih Wang, Yu-Ming Lin
  • Publication number: 20220231051
    Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.
    Type: Application
    Filed: August 11, 2021
    Publication date: July 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Shih-Lien Linus Lu, Chia-En Huang, Yih Wang, Yu-Ming Lin
  • Publication number: 20220223712
    Abstract: The present disclosure provides a semiconductor device and a method for forming a semiconductor device. The semiconductor device includes a substrate, and a first gate dielectric stack over the substrate, wherein the first gate dielectric stack includes a first ferroelectric layer, and a first dielectric layer coupled to the first ferroelectric layer, wherein the first ferroelectric layer includes a first portion made of a ferroelectric material in orthorhombic phase, a second portion made of the ferroelectric material in monoclinic phase, and a third portion made of the ferroelectric material in tetragonal phase, wherein a total volume of the second portion is greater than a total volume of the first portion and the total volume of the first portion is greater than a total volume of the third portion.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Inventors: CHUN-YEN PENG, TE-YANG LAI, BO-FENG YOUNG, CHIH-YU CHANG, SAI-HOOI YEONG, CHI ON CHUI
  • Patent number: 11387351
    Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Che-Cheng Chang, Po-Chi Wu
  • Patent number: 11386820
    Abstract: A method of detecting threshold voltage shift and a threshold voltage shift detection device are provided. The method is applied to a pixel driving circuit which I is electrically coupled to a control line, a voltage line and a detection node, respectively. The method includes: in a detection cycle including a setting phase and a detection phase, in the setting phase, controlling a transistor included in the pixel driving circuit to be in a biased state; in the detection phase, providing a preset control voltage signal to the control line, providing a preset voltage signal to the voltage line, and determining a threshold voltage shift state of the transistor according to an electric potential of the detection node.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: July 12, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guangyao Li, Dongfang Wang, Jun Wang, Haitao Wang, Chaowei Hao, Bo Feng, Rong Liu, Wei Cai, Biao Luo, Xuechao Sun, Xuehai Gui, Qibin Liang, Yanfei Wan, Jin Su
  • Publication number: 20220216365
    Abstract: A manufacturing method of an electronic element module is provided. The method includes: disposing a plurality of first microelectronic elements on a first temporary substrate; and replacing at least one defective microelectronic element of the first microelectronic elements with at least one second microelectronic element. The first microelectronic elements and at least one second microelectronic element are distributed on the first temporary substrate. The first microelectronic elements and at least one second microelectronic element have same properties, and at least one of the appearance difference, the height difference and the orientation difference exists between the first microelectronic elements and at least one second microelectronic element. A semiconductor structure and a display panel are also provided.
    Type: Application
    Filed: May 19, 2021
    Publication date: July 7, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Bo-Wei Wu, Yu-Yun Lo, Chien-Chen Kuo, Chang-Feng Tsai, Tzu-Yang Lin
  • Patent number: 11378856
    Abstract: A display substrate includes: a base substrate, as well as a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a common electrode metal layer laminated on one side of the base substrate. The common electrode metal layer includes metal line segments and connecting line segments. The metal line segments include first metal line segments and second metal line segments. The connecting line segments connect the adjacent first and second metal line segments. Each connecting line segment is provided with a maintenance line segment. Orthographic projections of the maintenance line segments on the base substrate do not overlap those of gate lines and data lines on the base substrate. The spacing between the orthographic projections of the maintenance line segments and those of the gate lines and data lines is greater than or equal to a preset distance, which is greater than zero.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: July 5, 2022
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chen Lin, Jinliang Wang, Yisong Ruan, Bo Wang, Shujuan Li, Zhangxiang Huang, Liangzhen Lin, Xi Chen, Yuchun Feng, Qian Zhang, Bin Yue
  • Publication number: 20220208990
    Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Inventors: Bo-Feng Young, Chih-Yu Chang, Sai-Hooi Yeong, Chi On Chui, Chih-Hao Wang
  • Patent number: 11362108
    Abstract: The present disclosure provides a semiconductor structure, including: a first layer including a logic device; and a second layer over the first layer, including a first type memory device, a though silicon via (TSV) electrically connecting the logic device and the first type memory device. A method of forming semiconductor structure is also disclosed.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 14, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Bo-Feng Young, Han-Jong Chia, Sai-Hooi Yeong, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20220181495
    Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 9, 2022
    Inventors: CHUN-YEN PENG, CHIH-YU CHANG, BO-FENG YOUNG, TE-YANG LAI, SAI-HOOI YEONG, CHI ON CHUI
  • Patent number: 11355551
    Abstract: A magnetic tunnel junction memory device includes a vertical stack of magnetic tunnel junction NOR strings located over a substrate. Each magnetic tunnel junction NOR string includes a respective semiconductor material layer that contains a semiconductor source region, a plurality of semiconductor channels, and a plurality of semiconductor drain regions, a plurality of magnetic tunnel junction memory cells having a respective first electrode that is located on a respective one of the plurality of semiconductor drain regions, and a metallic bit line contacting each second electrode of the plurality of magnetic tunnel junction memory cells. The vertical stack of magnetic tunnel junction NOR strings may be repeated along a channel direction to provide a three-dimensional magnetic tunnel junction memory device.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Han-Jong Chia, Bo-Feng Young, Sai-Hooi Yeong, Chenchen Jacob Wang, Meng-Han Lin, Yu-Ming Lin
  • Publication number: 20220173252
    Abstract: A semiconductor device and method of manufacture are provided which utilizes metallic seeds to help crystallize a ferroelectric layer. In an embodiment a metal layer and a ferroelectric layer are formed adjacent to each other and then the metal layer is diffused into the ferroelectric layer. Once in place, a crystallization process is performed which utilizes the material of the metal layer as seed crystals.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 2, 2022
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chi On Chui