Patents by Inventor Bo Feng

Bo Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12363894
    Abstract: A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.
    Type: Grant
    Filed: February 1, 2024
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chih-Yu Chang, Han-Jong Chia, Chenchen Jacob Wang, Yu-Ming Lin
  • Publication number: 20250196733
    Abstract: An automobile safety seat and a child stroller is provided. The automobile safety seat includes a base, a stroller frame being folded and arranged on the base, a carrycot arranged on the stroller frame, a first locking mechanism for locking the carrycot on the stroller frame being folded, a second locking mechanism also for locking the carrycot on the stroller frame being folded, and a third locking mechanism for locking the stroller frame on the base. An engaging and disengaging device is arranged between the first locking mechanism and the second locking mechanism, when the engaging and disengaging device is in an operating state of engaging, the first locking mechanism and the second locking mechanism are connected such that the first locking mechanism and the second locking mechanism are synchronously in a locking state or an unlocking state.
    Type: Application
    Filed: February 28, 2025
    Publication date: June 19, 2025
    Inventors: Bo FENG, Xiaoyong YANG
  • Publication number: 20250180764
    Abstract: A data processing method for static computed tomography scanning and a device are provided. The data processing method for static CT scanning includes: performing, in response to receiving a beam synchronization pulse signal, a time synchronization on N angle pulse signals and a time synchronization on N belt pulse signals by using the beam synchronization pulse signal, to obtain N synchronization angle pulse signals and N synchronization belt pulse signals, respectively; generating N timestamps based on the N synchronization angle pulse signals and the N synchronization belt pulse signals, where the N timestamps correspond to N scanning imaging systems of a static CT scanning device, respectively, and each of the N timestamps includes angle data and belt data; and packaging beam data, detection data, the angle data, and the belt data corresponding to each of the N scanning imaging systems to obtain N data packets.
    Type: Application
    Filed: December 5, 2024
    Publication date: June 5, 2025
    Inventors: Zhiqiang CHEN, Li Zhang, Yuanjing Li, Qingping Huang, Bo Feng, Xianguo Zheng, Zhenhua Zhao, Pengfei Xing
  • Patent number: 12324146
    Abstract: Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi On Chui
  • Publication number: 20250169068
    Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.
    Type: Application
    Filed: January 21, 2025
    Publication date: May 22, 2025
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Patent number: 12300190
    Abstract: Provided is a driving method of a display panel, which relates to a field of a display technology. The display panel includes a pixel array, the pixel array comprises a plurality of rows of sub-pixels, and the driving method includes: driving, in a same display frame, different sub-pixels in a row of the sub-pixels respectively by a forward driving signal and a negative driving signal, wherein a voltage conversion rate of the forward driving signal is greater than a voltage conversion rate of the negative driving signal under a same display gray scale. A driving circuit, a driving chip and a display device are further provided.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: May 13, 2025
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chongguang Wei, Weifan Yang, Lu Ding, Linlin Wang, Bo Feng, Xiaofeng Yin
  • Patent number: 12302636
    Abstract: A method for forming a memory device includes: forming a first layer stack and a second layer stack successively over a substrate, wherein each of the first and the second layer stacks comprises a dielectric layer, a channel layer, and a source/drain layer formed successively over the substrate; forming openings that extend through the first layer stack and the second layer stack, where the openings include first openings within boundaries of the first and the second layer stacks, and a second opening extending from a sidewall of the second layer stack toward the first openings; forming inner spacers by replacing portions of the source/drain layer exposed by the openings with a dielectric material; lining sidewalls of the openings with a ferroelectric material; and forming first gate electrodes in the first openings and a dummy gate electrode in the second opening by filling the openings with an electrically conductive material.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Bo-Feng Young, Yu-Ming Lin, Han-Jong Chia
  • Patent number: 12293999
    Abstract: Routing arrangements for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a memory array including a gate dielectric layer contacting a first word line and a second word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, the gate dielectric layer being disposed between the OS layer and each of the first word line and the second word line; an interconnect structure over the memory array, a distance between the second word line and the interconnect structure being less than a distance between the first word line and the interconnect structure; and an integrated circuit die bonded to the interconnect structure opposite the memory array, the integrated circuit die being bonded to the interconnect structure by dielectric-to-dielectric bonds and metal-to-metal bonds.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Patent number: 12289892
    Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, a transistor, and a memory cell. The substrate has a semiconductor device and a dielectric structure disposed on the semiconductor device. The transistor is disposed over the dielectric structure and is electrically coupled with the semiconductor device. The semiconductor device includes a gate, a channel layer, source drain regions, and a stack of a gate dielectric layer and a first ferroelectric layer. The gate and the source and drain regions are disposed over the dielectric structure. The channel layer is located between the source and drain regions. The stack of the gate dielectric layer and the first ferroelectric layer is disposed between the gate and the channel layer. The memory cell is disposed over the transistor and is electrically connected to one of the source and drain regions. The memory cell includes a ferromagnetic layer or a second ferroelectric layer.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Yu-Ming Lin, Chao-I Wu, Mauricio Manfrini
  • Patent number: 12289893
    Abstract: A semiconductor device includes a first electrode layer, a ferroelectric layer, a first alignment layer and a second electrode layer. A material of the first alignment layer includes rare-earth metal oxide. The ferroelectric layer and the first alignment layer are disposed between the first electrode layer and the second electrode layer, and the first alignment layer is disposed between the ferroelectric layer and the first electrode layer.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Qing Shi, Bo-Feng Young, Yu-Chuan Shih, Sai-Hooi Yeong, Blanka Magyari-Kope, Ying-Chih Chen, Tzer-Min Shen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12284810
    Abstract: A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Han-Jong Chia, Feng-Cheng Yang, Bo-Feng Young, Nuo Xu, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 12276877
    Abstract: Provided is an array substrate. The array substrate includes: a base substrate, and a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels and a plurality of touch signal lines disposed on the base substrate. The data lines have a plurality of first extending parts and a plurality of second extending parts which are in an alternating arrangement. When the array substrate is used to prepare a liquid crystal display panel and the liquid crystal display panel is displaying, in each column of the sub-pixels, the voltage polarities of the two adjacent sub-pixels which respectively belong to two adjacent first pixel regions are opposite.
    Type: Grant
    Filed: February 7, 2024
    Date of Patent: April 15, 2025
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bo Feng, Shijun Wang, Yang Wang, Zhan Wei, Wenkai Mu, Yi Liu, Li Tian
  • Patent number: 12263633
    Abstract: A nylon tube automatic thermoforming apparatus includes a main body, a conveying assembly, a heating assembly and a tube bending assembly. The heating assembly includes an oven communicated with the conveying assembly and an electrically heated cylinder arranged between the oven and the tube bending assembly. A heating coil is arranged in the electrically heated cylinder. A nylon tube is conveyed from the conveying assembly and enters the tube bending assembly via the oven and the heating coil. The electrically heated cylinder and the tube bending assembly are arranged outside the main body. A nylon tube shaping process includes the steps of drawing, heating inside a main body, heating outside the main body, bending, staying, feeding, angle adjusting, repeating the above steps until the length and the curvature of the nylon tube meet the requirements, and cutting off.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: April 1, 2025
    Assignee: ZHEJIANG BOSHITE GROUP CO., LTD.
    Inventors: Bo Feng, Longjun He
  • Patent number: 12256550
    Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Meng-Han Lin, Chih-Yu Chang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 12245436
    Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chenchen Jacob Wang, Bo-Feng Young, Yu-Ming Lin, Chi On Chui, Sai-Hooi Yeong
  • Publication number: 20250070594
    Abstract: The present invention discloses a disaster prevention, early warning and production decision support method and system for a power distribution network, and relates to the technical field of the power distribution network. Various data is fused, a maximum wind load, a lightning trip-out rate, a maximum carrying capacity at a highest operation temperature and an average failure frequency and time under an environmental factor are calculated, and a power outage risk is evaluated and classified; and after an emergency, a power grid topology is analyzed, and a device outage probability is calculated to obtain a load power outage probability and risk and provide disaster early warning, monitoring and rush repair decision support.
    Type: Application
    Filed: November 12, 2024
    Publication date: February 27, 2025
    Inventors: Wei ZHANG, Shan LI, Yangsheng LIU, Weixiang HUANG, Zongtao QIN, Bo FENG, Jianna OUYANG, Rongrong WU
  • Publication number: 20250072002
    Abstract: A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Yu-Ming Lin, Chi On Chui
  • Patent number: 12238926
    Abstract: In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Publication number: 20250058841
    Abstract: A transmission mechanism of a micro crawling robot and the micro crawling robot. The transmission mechanism is a parallel mechanism with three branch chains and two degrees of freedom, and comprises: a fixed platform; a moving platform; a constraint limb comprising a first rotating joint S11 and a second rotating joint S12, which generate the functions of restraining the lifting motion and the twisting motion of the moving platform, respectively; a first actuation limb comprising third to seventh rotating joints S21-S25, wherein the third rotating joint S21 is a actuation joint and the rest are transmission rotating joints; and a second actuation limb comprising eighth to twelfth rotating joints S31-S35, wherein the eighth rotating joint S31 is a actuation joint, and the rest are the transmission rotating joints.
    Type: Application
    Filed: November 6, 2024
    Publication date: February 20, 2025
    Inventors: Yide LIU, Shaoxing QU, Yanhong CHEN, Bo FENG, Dongqi WANG
  • Patent number: D1067338
    Type: Grant
    Filed: May 9, 2024
    Date of Patent: March 18, 2025
    Assignee: Xiamen Murao Technology Co., Ltd.
    Inventor: Bo Feng