Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack includes a ferroelectric gate dielectric layer. An amorphous high-k dielectric layer and a dopant-source layer are deposited sequentially followed by a post-deposition anneal (PDA). The PDA converts the amorphous high-k layer to a polycrystalline high-k film with crystalline grains stabilized by the dopants in a crystal phase in which the high-k dielectric is a ferroelectric high-k dielectric. After the PDA, the remnant dopant-source layer may be removed. A gate electrode is formed over remnant dopant-source layer (if present) and the polycrystalline high-k film.

Abstract: Gates having air gaps therein, and methods of fabrication thereof, are disclosed herein. An exemplary gate includes a gate electrode and a gate dielectric. A first air gap is between and/or separates a first sidewall of the gate electrode from the gate dielectric, and a second air gap is between and/or separates a second sidewall of the gate electrode from the gate dielectric. A dielectric cap may be disposed over the gate electrode, and the dielectric cap may wrap a top of the gate electrode. The dielectric cap may fill a top portion of the first air gap and a top portion of the second air gap. The gate may be disposed between a first epitaxial source/drain and a second epitaxial source/drain, and a width of the gate is about the same as a distance between the first epitaxial source/drain and the second epitaxial source/drain.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is vertically disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. An area of the gate stack projected on a top surface of the substrate is within an area of the bottom dielectric layer projected on the top surface of the substrate.

Abstract: A memory device including a word line, a source line, a bit line, a memory layer, a channel material layer is described. The word line extends in a first direction, and liner layers disposed on a sidewall of the word line. The memory layer is disposed on the sidewall of the word line between the liner layers and extends along sidewalls of the liner layers in the first direction. The liner layers are spaced apart by the memory layer, and the liner layers are sandwiched between the memory layer and the word line. The channel material layer is disposed on a sidewall of the memory layer. A dielectric layer is disposed on a sidewall of the channel material layer. The source line and the bit line are disposed at opposite sides of the dielectric layer and disposed on the sidewall of the channel material layer. The source line and the bit line extend in a second direction perpendicular to the first direction. A material of the liner layers has a dielectric constant lower than that of a material of the memory layer.

Abstract: The present disclosure provides fingerprint recognition substrate including fingerprint recognition units arranged in array, signal reading line groups and gating circuits, fingerprint recognition units are divided into first fingerprint recognition groups arranged along row direction, first fingerprint recognition groups, signal reading line groups and gating circuits are in one-to-one correspondence with one another; first fingerprint recognition group includes fingerprint recognition units consecutively arranged in row direction, signal reading line group includes signal reading lines each coupled to corresponding column of fingerprint recognition units; gating circuit includes switch circuits each coupled to one signal transmission channel on signal receiving unit through corresponding switch circuit; among all signal reading lines, different signal reading lines in same signal reading line group are coupled to different signal transmission channels, and at least two signal reading lines in different sign

Abstract: A ferroelectric tunnel junction (FTJ) memory device includes a bottom electrode located over a substrate, a top electrode overlying the bottom electrode, and a ferroelectric tunnel junction memory element located between the bottom electrode and the top electrode. The ferroelectric tunnel junction memory element includes at least one ferroelectric material layer and at least one tunneling dielectric layer.

Abstract: Provided is a display substrate. The display substrate includes a base substrate, a plurality of gate lines, a plurality of data lines, and a plurality of rows of pixels arranged in an array on the base substrate, and a plurality of shift circuits disposed on the base substrate, wherein in a plurality of pixels connected to each shift circuit, the respective pixels sharing the same data line have the same color, and each shift circuit is connected to one turn-on signal terminal.

Abstract: A method of image quality assessment, performed by one or more processors in an image capture device, is disclosed. The method comprising receiving notification of capture of an image and in response, initiating an image assessment task to assess the quality of the image. The assessment task comprises determining suitability of the image for image quality assessment, running an image quality assessment model on the image to generate image quality assessment results, collecting data related to the capture of the image, and transmitting the results to an image quality assessment repository. The image assessment task may be a lower priority asynchronous task.

Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

Abstract: A device includes a substrate, gate stacks, source/drain (S/D) features over the substrate, S/D contacts over the S/D features, and one or more dielectric layers over the gate stacks and the S/D contacts. A via structure penetrates the one or more dielectric layers and electrically contacts one of the gate stacks and the S/D contacts. And a ferroelectric (FE) stack is over the via structure and directly contacting the via structure, wherein the FE stack includes an FE feature and a top electrode over the FE feature.

Abstract: A semiconductor device includes: a fin protruding above a substrate; source/drain regions over the fin; nanosheets between the source/drain regions, where the nanosheets comprise a first semiconductor material; inner spacers between the nanosheets and at opposite ends of the nanosheets, where there is an air gap between each of the inner spacers and a respective source/drain region of the source/drain regions; and a gate structure over the fin and between the source/drain regions.

Abstract: The fingerprint recognition panel includes fingerprint recognition circuits arranged in a matrix, reading signal lines, a gate driving circuit and scanning lines connected with the gate driving circuit. The gate driving circuit is for outputting scanning signals to the scanning lines successively; each fingerprint recognition circuit is in connection with two scanning lines, a reading control end is connected with a first scanning line, and a reset control end is connected with a second scanning line; the first scanning line in connection with the fingerprint recognition circuits of the nth row and the second scanning line in connection with the fingerprint recognition circuits of the (n?m)th row are the same; or the second scanning line in connection with the fingerprint recognition circuits of the nth row and the first scanning line in connection with the fingerprint recognition circuits of the (n?m)th row are the same.

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a bottom dielectric layer, and a gate stack. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The bottom dielectric layer is vertically disposed between the at least one fin and the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. An area of the gate stack projected on a top surface of the substrate is within an area of the bottom dielectric layer projected on the top surface of the substrate.

Abstract: The present disclosure, in some embodiments, relates to a ferroelectric memory device. The ferroelectric memory device includes a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. A plurality of oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

Abstract: A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

Abstract: The present disclosure provides a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes a substrate, a metal gate layer over the substrate, a channel between a source region and a drain region in the substrate, and a ferroelectric layer, at least a portion of the ferroelectric layer is between the metal gate layer and the substrate, wherein the ferroelectric layer includes hafnium oxide-based material, the hafnium oxide-based material includes a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase, wherein a first volume of the first portion is greater than a second volume of the second portion, and the second volume of the second portion is greater than a third volume the third portion.

Abstract: A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.

Abstract: A smoothly adjustable display screen bracket comprises: a first connecting seat, a connecting rod group and a second connecting seat, wherein the connecting rod group is arranged between the first connecting seat and the second connecting seat, the connecting rod group comprises a connecting rod, a force applying mechanism, a limiting sleeve, a cam member and a roller, and the roller is rotatably arranged on the second connecting seat, and one end of the force applying mechanism is connected with the first connecting seat, and the other end of the force applying mechanism is connected with the cam member, wherein a curved surface of the cam member is configured to press against the roller under the pushing action of the force applying mechanism. The limiting sleeve covers the outside of the force applying mechanism.

Abstract: Circuit devices and methods of forming the same are provided. In one embodiment, a method includes receiving a workpiece that includes a substrate and a fin extending from the substrate, forming a first ferroelectric layer on the fin, forming a dummy gate structure over a channel region of the fin, forming a gate spacer over sidewalls of the dummy gate structure, forming an inter-level dielectric layer over the workpiece, removing the dummy gate structure to expose the first ferroelectric layer over the channel region of the fin, and forming a gate electrode over the exposed first ferroelectric layer over the channel region of the fin.