Abstract: This disclosure relates to the technical field of marine environment prediction, and in particular, to a method and system for multimodal fusion prediction of a marine environment based on digital twinning. The method includes the following steps: capturing spatiotemporal correlation features of multimodal data of the marine environment based on a dynamic multimodal graph neural network; performing multi-scale feature fusion on the spatiotemporal correlation features by using a multi-scale gating unit to obtain a comprehensive feature representation; predicating the comprehensive feature representation by using a hybrid time-series prediction framework to obtain preliminary marine environment prediction data, including short-term dynamic modeling and long-term trend modeling; and performing noise fitting on the preliminary marine environment prediction data by using a generative adversarial network to generate the final marine environment prediction data.

Abstract: A semiconductor structure and its fabrication method. First sacrificial layers are formed on a base substrate. Channel structures are formed on the first sacrificial layers. Each channel structure includes stacked channel stack layer(s). Each channel stack layer includes a second sacrificial layer and a channel layer. Dummy gate structures crossing the channel structures are also formed on the base substrate. Etching resistance of the first sacrificial layers is smaller than etching resistance of the second sacrificial layers. The channel structures and the first sacrificial layers on two sides of each dummy gate structure are removed to form first grooves. The first sacrificial layers at the bottoms of the channel structures are removed to form second grooves connected to the first grooves. Isolation layers are formed in the second grooves; and source-drain doping layers are formed in the first grooves.

Abstract: Semiconductor structure and forming method thereof are provided. The semiconductor structure includes a substrate and a plurality of transistors located over the substrate. A transistor of the plurality of transistors includes: a channel layer parallel to a substrate surface, a gate structure surrounding the channel layer, and a source/drain doped region located on two sides of the gate structure. The source/drain doped region is in contact with the channel layer, and the gate structure is electrically isolated from the source/drain doped region. The semiconductor structure also includes a first metal structure located over the substrate, and a second metal structure located over the first metal structure and the gate structure. The first metal structure is in contact with the source/drain doped region. The first metal structure, the source/drain doped region and the gate structure are arranged along a first direction. The first direction is parallel to the substrate surface.

Abstract: Semiconductor structure and forming method thereof are provided. The forming method includes: providing a substrate; forming a plurality of initial composite layers on a portion of the substrate; forming a plurality of source and drain layers on surfaces of the plurality of channel layers exposed by a first opening and grooves by using a selective epitaxial growth process, the plurality of source and drain layers being parallel to a first direction and distributed along a second direction, the second direction being parallel to a normal direction of the substrate, and gaps being between adjacent source and drain layers; forming contact layers on surfaces of the plurality of source and drain layers and in the gaps; and forming a conductive structure on a surface of a contact layer on a source and drain layer of the plurality of source and drain layers.

Abstract: The present invention involves the technology field of surfactant, which provides a high-molecular non-ion surfactant and preparation methods and use thereof. The high-molecular non-ion surfactant has o-dihyoxybenzene group, showing a strong adhesion ability. Its surface activity performance and adhesion performance can be regulated by adjusting the type and proportion of raw materials. The preparation method of the high-molecular non-ion surfactant is simple and low in cost, and it is easy to industrialize. In addition, the high-molecular non-ion surfactant can also be applied to prepare herbicide, fungicide, acaricide, and insecticide.

Abstract: Devices, systems, and methods for using middleware to manage licenses to applications on intelligent electronic devices (IEDs) for power system equipment. A middleware device may identify activation codes for IEDs of a power system; identify hardware signatures of the IEDs; send a license request, using a software development kit (SDK) application programming interface (API) of the middleware device, to a licensing server or using a web portal to the licensing server, the license request comprising a first activation code of the activation codes and a first hardware signature of a first IED of the IEDs; identify a response file received based on the license request; establish a secure connection with the first IED based on receiving the response file; validate, activate, and extract features from a first license for the first IED based on the response file; and send, using the SDK API, the features to the first IED.

Abstract: Devices, systems, and methods for platform capability description (PCD) file-based configuring of intelligent electronic devices (IEDs) may include generating, by at least one processor, PCD files for an IED, the PCD files defining the capabilities of the IED, a license of functions of the IED for a user, and rules applying to settings of the IED; generating, using an IED configurator tool from which IED rules are absent, based on the PCD files, a bundle of files for the IED, the bundle comprising a manifest and configuration files for the IED; and providing, by the IED configurator tool, to the IED, the bundle, the license of functions, and the rules, wherein the IED is configured based on the bundle, the license of functions, and the rules.

Abstract: Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

Abstract: The present disclosure discloses a shoulder joint prosthesis containing zirconium-niobium alloy on oxidation layer and a preparation method thereof, the preparation method comprises: using zirconium-niobium alloy powder as a raw material, conducting a 3D printing for one-piece molding to obtain an intermediate products of the humeral handle with articular surface and the scapular glenoid plate, and performing Sinter-HIP, cryogenic cooling and surface oxidation to obtain humeral handle with articular surface and scapular glenoid plate. The prosthesis comprises a humeral handle, an articular surface, a humeral head and a scapular glenoid plate, a bone trabeculae is arranged on the outer surface of the upper part of the humeral handle, the upper surface of the scapular glenoid plate and the outer surface of the circular pipe with internal thread.

Abstract: The present disclosure provides a zero-shot low-dose Computed Tomography (CT) image denoising method and apparatus based on strip diffusion model. This method includes building a strip diffusion model which uses high fidelity of the diffusion model to complete end-to-end denoising of low-dose CT images with different doses, thicknesses and devices. Particularly, in the training process, only the normal-dose CT images are required, greatly reducing the data reliance of the model, and model training across dose and thickness condition can be carried out with the data of only one scenario. In a sampling process, strip scanning strategy is used in combination with overlapped strip information and the input low-dose CT images to solve the maximum a posteriori problem, thereby sequentially generating denoising results. The present disclosure only uses simple convolution and attention architecture and carries out extensive experiments on the datasets involving different doses and thicknesses.

Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, a dummy gate structure, a source-drain doped region, and an interlayer dielectric layer; removing the dummy gate structure located at an isolation region to form an isolation opening; performing first ion doping on a fin below the isolation opening, to form an isolation doped region, where a doping type of the isolation doped region is different from a doping type of the source-drain doped region; filling an isolation structure in the isolation opening; removing the remaining dummy gate structure, to form a gate opening; and forming a gate structure in the gate opening.

Abstract: A semiconductor structure includes: a channel protrusion structure, suspended on a base, including channel layers arranged at intervals along a longitudinal direction; a gate structure, spanning the channel protrusion structure and covering part of a top and part of a side wall of the channel protrusion structure, surrounding and covering the channel layers, the gate structure located between adjacent channel layers in the longitudinal direction and between adjacent channel layers and the base serving as an inner gate structure, and the inner gate structure and the adjacent channel layers, and/or, the inner gate structure, the adjacent channel layers and the base forming an inner trench; an inner spacer, located in the inner trench; and a source/drain doped layer, located on the base and connected to two ends of the channel layer, the source/drain doped layer and the inner spacer having a gap therebetween used as an air spacer.

Abstract: A semiconductor structure and its fabrication method. First sacrificial layers are formed on a base substrate. Channel structures are formed on the first sacrificial layers. Each channel structure includes stacked channel stack layer(s). Each channel stack layer includes a second sacrificial layer and a channel layer. Dummy gate structures crossing the channel structures are also formed on the base substrate. Etching resistance of the first sacrificial layers is smaller than etching resistance of the second sacrificial layers. The channel structures and the first sacrificial layers on two sides of each dummy gate structure are removed to form first grooves. The first sacrificial layers at the bottoms of the channel structures are removed to form second grooves connected to the first grooves. Isolation layers are formed in the second grooves; and source-drain doping layers are formed in the first grooves.

Abstract: Semiconductor structure and forming method thereof are provided. The semiconductor structure includes a substrate and a plurality of transistors located over the substrate. A transistor of the plurality of transistors includes: a channel layer parallel to a substrate surface, a gate structure surrounding the channel layer, and a source/drain doped region located on two sides of the gate structure. The source/drain doped region is in contact with the channel layer, and the gate structure is electrically isolated from the source/drain doped region. The semiconductor structure also includes a first metal structure located over the substrate, and a second metal structure located over the first metal structure and the gate structure. The first metal structure is in contact with the source/drain doped region. The first metal structure, the source/drain doped region and the gate structure are arranged along a first direction. The first direction is parallel to the substrate surface.

Abstract: A semiconductor structure includes a substrate, channel layers arranged in parallel along a first direction, gate structures arranged in parallel along a second direction, source doped regions and drain doped regions located on two sides of the gate structures respectively, and a metal layer. The gate structures surround the channel layers, respectively. The first and second directions are parallel to a substrate surface and perpendicular to each other. The source and drain doped regions contact the channel layers, respectively. The metal layer contacts one of the source or drain doped regions. The metal layer, one of the source doped regions, one of the drain doped regions, and one of the gate structures are stacked along the second direction.

Abstract: A semiconductor structure and a formation method of the semiconductor structure are provided in the present disclosure. The semiconductor structure includes a substrate, including a first device region and a second device region; a first device layer on the substrate, where a first transistor at the first device region is in the first device layer; a second device layer on the first device layer, where a second transistor at the second device region is in the second device layer, and projections of the first transistor and the second transistor on a surface of the substrate are non-overlapped with each other; and an electrical interconnection structure in the first device layer and the second device layer, where the electrical interconnection structure is electrically connected to each of the first transistor and the second transistor.

Abstract: A cooking device, which includes: a frame; a base, connected to the frame; a pot assembly, including a pot, the pot being configured to be connected to the base; a first seasoning mechanism, disposed on the frame, the first seasoning mechanism being capable of conveying solid materials into the pot; and a second seasoning mechanism, disposed on the frame, the second seasoning mechanism being capable of conveying liquid materials into the pot. During a cooking process, the cooking device may respectively put the solid materials and the liquid materials into the pot by using the first seasoning mechanism and the second seasoning mechanism, so as to replace manual material feeding. Therefore, the problems in the related art of long cooking time during the using of an automatic cooking machine by a user and poor user experience are solved, thereby improving user experience.

Abstract: A semiconductor structure includes a plurality of composite layers formed on a portion of a substrate. An interlayer dielectric layer is formed on the substrate and the plurality of composite layers. A first gate trench is formed on the interlayer dielectric layer, and a gate sidewall is formed on a side surface of the first gate trench. The composite layer includes stacked channel layers and a second gate trench between neighboring channel layers. The first gate trench and the gate sidewall cross over a portion of a sidewall and a portion of a top surface of the composite layer, and the first gate trench communicates with the second gate trench. A gate is formed in the first and second gate trenches. The doping region is formed in a channel layer. The source-drain layer is formed in the composite layer on two sides of the gate structure.

Abstract: Semiconductor structure and formation method are provided. A method of forming a semiconductor structure includes providing a dielectric layer on a substrate, the dielectric layer including a first region and a second region under the first region, the first region including discrete first initial nanowires, and the second region including discrete second initial nanowires; etching the dielectric layer and the first initial nanowires in the first region to form a first opening in the first region, and forming first nanowires from the first initial nanowires; etching the dielectric layer at a bottom of the first opening and the second initial nanowires to form a second opening in the second region, and forming second nanowires from the second initial nanowires; forming a second source/drain layer in the second opening; forming an isolation layer on the second source/drain layer; and forming a first source/drain layer in the first opening.

Abstract: Semiconductor structures and methods for forming the same are provided.