Patents by Inventor Bo Su
Bo Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230238449Abstract: A semiconductor structure and a forming method therefor are provided. The forming method includes: providing a base, a gate structure, a source/drain doped area, and a bottom dielectric layer; forming a source/drain interconnect layer running through the bottom dielectric layer on a top of the source/drain doped area; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact running through the top dielectric layer on a top of the gate structure and a source/drain contact running through the top dielectric layer on a top of the source/drain interconnect layer; forming a sacrificial side wall layer on side walls of the gate contact and the source/drain contact; forming a gate plug filling the gate contact and a source/drain plug filling the source/drain contact; removing the sacrificial side wall layer to form a first gap; and forming a sealing layer sealing the first gap.Type: ApplicationFiled: March 22, 2023Publication date: July 27, 2023Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Bo SU, Hansu OH
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Publication number: 20230223452Abstract: A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.Type: ApplicationFiled: March 21, 2023Publication date: July 13, 2023Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Bo Su, Hansu OH, Chunsheng ZHENG, Erhu ZHENG, Haiyang ZHANG
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Publication number: 20230194899Abstract: An integrated binocular augmented reality smart glass, which comprises an integrated structure of glass temples, an imaging system, a nose pad, a battery module and a glass frame, and a circuit board processor module and a control system are integrated therein. The integrated binocular augmented reality smart glass has a small volume, a light weight and a strong mobile flexibility and is convenient in usage and interaction, and can be worn stably for a long time under various application scenarios without generating discomfort. The imaging system of the integrated binocular augmented reality smart glass is a multi-layer structure, and comprises filter glasses, display glasses and functional glasses, where the filter glasses and the functional glasses are respectively located at two sides of the display glasses and are mounted on the glass frame.Type: ApplicationFiled: March 8, 2017Publication date: June 22, 2023Inventors: BO SU, YOUCHU WANG
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Publication number: 20230181292Abstract: Provided is a surface-treated implant structure. The implant structure according to an aspect includes a fixture acting as an artificial tooth root, and the nano-protrusions included in the outer peripheral surface of the fixture exhibit a certain level of height, depth, and aspect ratio.Type: ApplicationFiled: November 30, 2021Publication date: June 15, 2023Applicant: B2LAB CO.,LTD.Inventors: Bo Su JEONG, Byung Hak LEE
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Patent number: 11664227Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes providing a to-be-etched layer; forming an initial mask layer over the to-be-etched layer; forming a patterned structure, on the initial mask layer and exposing a portion of the initial mask layer; forming a barrier layer on a sidewall surface of the patterned structure; using the patterned structure and the barrier layer as a mask, performing an ion doping process on the initial mask layer to form a doped region and an un-doped region between doped regions in the initial mask layer; removing the patterned structure and the barrier layer; and forming a mask layer on a top surface of the to-be-etched layer by removing the un-doped region. The mask layer includes a first opening exposing the top surface of the to-be-etched layer.Type: GrantFiled: September 17, 2020Date of Patent: May 30, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Qian Jiang Zhang, Bo Su, Tao Dou, Lin Lin Sun
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Publication number: 20230149402Abstract: The present invention relates to a solid pharmaceutical preparation and a preparation method therefor. Specifically, disclosed are a solid pharmaceutical preparation that comprises an orexin receptor antagonist compound and a preparation method therefor, the solid pharmaceutical preparation comprising an active ingredient of a compound represented by formula I, a filler, a binder, a disintegrant, and a lubricant. The solid pharmaceutical preparation has good dissolution, stability and in vivo bioavailability.Type: ApplicationFiled: April 14, 2021Publication date: May 18, 2023Applicants: SHANGHAI HAIYAN PHARMACEUTICAL TECHNOLOGY CO., LTD., YANGTZE RIVER PHARMACEUTICAL GROUP CO., LTD.Inventors: Taotao JIANG, Jibiao WANG, Han YANG, Li LI, Zhaoling DAN, Keyi ZHU, Zhenya ZENG, Bo SU, Xi CHEN
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Publication number: 20230100058Abstract: Semiconductor structure and forming method thereof are provided. The forming method includes: providing a substrate; forming a plurality of initial composite layers on a portion of the substrate; forming a plurality of source and drain layers on surfaces of the plurality of channel layers exposed by a first opening and grooves by using a selective epitaxial growth process, the plurality of source and drain layers being parallel to a first direction and distributed along a second direction, the second direction being parallel to a normal direction of the substrate, and gaps being between adjacent source and drain layers; forming contact layers on surfaces of the plurality of source and drain layers and in the gaps; and forming a conductive structure on a surface of a contact layer on a source and drain layer of the plurality of source and drain layers.Type: ApplicationFiled: September 29, 2022Publication date: March 30, 2023Inventors: Hailong YU, Bo SU, Hansu OH
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Patent number: 11605726Abstract: A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region.Type: GrantFiled: April 9, 2021Date of Patent: March 14, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Hansu Oh, Pengchong Li, Xuejie Shi, Yiyu Chen, Bo Su
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Publication number: 20230027219Abstract: The present disclosure provides a mixture of sugar apple and rosemary extracts, optionally in combination with prickly ash extract, for use as skin care compositions.Type: ApplicationFiled: September 16, 2022Publication date: January 26, 2023Applicant: Unigen, Inc.Inventors: Lidia Alfaro Brownell, Min Chu, Brandon Corneliusen, Mei-Feng Hong, Ji-Hye Hwang, Eu-Jin Hyun, Qi Jia, Ping Jiao, Mi-Ran Kim, Bo-Su Lee, Young-Chul Lee, Jeong-Bum Nam, Mi-Sun Oh, Mesfin Yimam
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Patent number: 11551924Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.Type: GrantFiled: July 22, 2020Date of Patent: January 10, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Shiliang Ji, Bo Su, Haiyang Zhang
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Patent number: 11538685Abstract: A method of forming a semiconductor structure includes providing a to-be-etched layer, forming a core layer over the to-be-etched layer, the core layer including a first trench extending along a first direction, forming a sidewall spacer layer on a top surface of the core layer and on sidewalls and a bottom surface of the first trench, forming a block cut structure in the first trench after forming the sidewall spacer layer, and after forming the block cut structure, etching back the sidewall spacer layer until exposing the top surface of the core layer, thereby leaving a sidewall spacer on the sidewalls of the first trench. The block cut structure extends through the first trench along a second direction. The second direction and the first direction are different. The block cut structure includes a first block-cut layer and a second block-cut layer.Type: GrantFiled: July 15, 2020Date of Patent: December 27, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Xiamei Tang, Wei Shi, Tao Dou, Bo Su, Youcun Hu
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Patent number: 11512040Abstract: A process for the preparation of amino alcohols includes condensing a compound of Formula (II), a stereoisomer, a tautomer, or a salt thereof with a compound of Formula (IIIa) or Formula (IIIb), a stereoisomer, a tautomer, or a salt thereof to form a condensation product; hydroxylating or acyloxylating the condensation product in the presence of an oxidant to obtain a hydroxylation or acyloxylation product; and subjecting the hydroxylation or acyloxylation product to one or more subsequent reactions comprising a hydrolysis reaction, alcohol deprotection, an amino lysis reaction, or a combination of two or more thereof to obtain an amino alcohol of Formula (I).Type: GrantFiled: July 2, 2019Date of Patent: November 29, 2022Assignees: BASF SE, BASF CORPORATION, THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Martin Ernst, Stephan Zuend, Bo Su, Ala Bunescu, John F. Hartwig
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Patent number: 11446225Abstract: The present disclosure provides a mixture of sugar apple and rosemary extracts, optionally in combination with prickly ash extract, for use as skin care compositions.Type: GrantFiled: March 30, 2020Date of Patent: September 20, 2022Assignee: Unigen, Inc.Inventors: Lidia Alfaro Brownell, Min Chu, Brandon Corneliusen, Mei-Feng Hong, Ji-Hye Hwang, Eu-Jin Hyun, Qi Jia, Ping Jiao, Mi-Ran Kim, Bo-Su Lee, Young-Chul Lee, Jeong-Bum Nam, Mi-Sun Oh, Mesfin Yimam
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Patent number: 11396312Abstract: A train overspeed protection method includes: acquiring, when emergency braking is triggered for a train, an initial speed limit location point of each speed limit region among a preset number of speed limit regions, and a first speed limit value corresponding to each initial speed limit location point so as to obtain a plurality of first speed limit values; acquiring a current traveling location point of the train and a corresponding second speed limit value, and acquiring a current traveling speed of the train; determining a plurality of decelerations of the current traveling speed relative to each first speed limit value, selecting a deceleration satisfying a preset condition from the plurality of decelerations, and determining the initial speed limit location point corresponding to the deceleration satisfying the preset condition as a target speed limit location point; determining an emergency braking speed according to a relative deceleration of the second speed limit value relative to the first speed liType: GrantFiled: December 20, 2017Date of Patent: July 26, 2022Assignee: BYD COMPANY LIMITEDInventors: Shengcong Ouyang, Bo Su, Faping Wang
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Patent number: 11393685Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.Type: GrantFiled: September 23, 2020Date of Patent: July 19, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Bo Su, Shiliang Ji, Erhu Zheng, Yan Wang, Haiyang Zhang
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Publication number: 20220199808Abstract: A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region.Type: ApplicationFiled: April 9, 2021Publication date: June 23, 2022Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Hansu OH, Pengchong LI, Xuejie SHI, Yiyu CHEN, Bo SU
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Publication number: 20220199460Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, a dummy gate structure, a source-drain doped region, and an interlayer dielectric layer; removing the dummy gate structure located at an isolation region to form an isolation opening; performing first ion doping on a fin below the isolation opening, to form an isolation doped region, where a doping type of the isolation doped region is different from a doping type of the source-drain doped region; filling an isolation structure in the isolation opening; removing the remaining dummy gate structure, to form a gate opening; and forming a gate structure in the gate opening.Type: ApplicationFiled: November 8, 2021Publication date: June 23, 2022Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Pengchong LI, Xuejie SHI, Hansu OH, Bo SU
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Publication number: 20220181482Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Inventors: Haiyang ZHANG, Bo SU
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Publication number: 20220124095Abstract: An authorized access list generation method including: at least one network service providing device registering for an authorized access list notification service with a server, the authorized access list including at least one authorization related record of at least one legitimate user device; the legitimate user device outputting a user ID to the server to log into the server, and directly sending an access request to a target network service provider after logging into the server, and continuing to provide an IP address being used and a device ID to the server to update a corresponding authorization related record; and the target network service providing device comparing the IP address, stored in each authorization related record of the authorized access list, with the IP address of a user device issuing an access request, and rejecting the access request if no matched result is found.Type: ApplicationFiled: January 4, 2021Publication date: April 21, 2022Inventors: Mao-Hung CHENG, Yu-Jui CHENG, Shih-Chan HUANG, Tong-Bo SU, Shih-Ming HU
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Patent number: 11309420Abstract: The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate having fins and forming an initial gate structure across the fins, which covers a portion of a top surface and sidewall surfaces of the fins, and includes an initial first region and an initial second region on the initial first region. A bottom boundary of the initial second region is higher than the top surface of the fins, and a size of the initial first region is larger than a size of the initial second region. A first etching process is performed on sidewalls of the initial gate structure to form a gate structure, which includes a first region formed by etching the initial first region, and a second region formed by etching the initial second region. A size of the first region is smaller than a size of the second region.Type: GrantFiled: February 20, 2020Date of Patent: April 19, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Haiyang Zhang, Bo Su