Patents by Inventor Bo-un Yoon

Bo-un Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6517412
    Abstract: A method of controlling a wafer polishing time using a sample-skip algorithm and a method of polishing a wafer using the same are provided. According to the method of controlling a wafer polishing time, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time &Dgr;t(n), to calculate the amount removed &Dgr;ToxP(n) from a polished layer on the wafer. The removal rate RRb(n) of a layer on a blanket wafer is calculated from the amount removed &Dgr;ToxP(n). A CMP time &Dgr;t(n+1) is determined for wafers of an n+1-th lot using the relationship equation &Dgr;t(n+1)={&Dgr;ToxT(n+1)+A}/RRb(n) where “A” is a constant and &Dgr;ToxT(n+1) is the target amount of a layer to be removed from a wafer of an n+1-th lot.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: February 11, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-dong Lee, Bo-un Yoon, Kyoung-mo Yang, Sang-rok Hah
  • Patent number: 6514862
    Abstract: A chemical mechanical polishing slurry includes an additive of a quaternary ammonium compound having a form of {N—(R1R2R3R4)}+X−, in which R1, R2, R3, and R4 are radicals, and X− is an anion derivative including halogen elements. Preferably, the quaternary ammonium compound is one of [(CH3)3NCH2CH2OH]Cl, [(CH3)3NCH2CH2OH]l, [(CH3)3NCH2CH2OH]Br, [(CH3)3NCH2CH2OH]CO3, and mixtures thereof. The slurry may further include a pH control agent formed of a base such as KOH, NH4OH, and (CH3)4NOH, and an acid such as HCl, H2SO4, H3PO4, and HNO3. Also, the pH control agent can include [(CH3)3NCH2CH2OH]OH. The slurry may further include a surfactant such as cetyldimethyl ammonium bromide, cetyldimethyl ammonium bromide, polyethylene oxide, polyethylene alcohol or polyethylene glycol.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: February 4, 2003
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Jae-dong Lee, Jong-won Lee, Bo-un Yoon, Sang-rok Hah
  • Publication number: 20030022499
    Abstract: A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.
    Type: Application
    Filed: April 5, 2001
    Publication date: January 30, 2003
    Inventors: Jong-Won Lee, Jae-Dong Lee, Bo-Un Yoon, Sang-Rok Hah
  • Publication number: 20020123224
    Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.
    Type: Application
    Filed: December 21, 2001
    Publication date: September 5, 2002
    Inventors: Jae-dong Lee, Bo-un Yoon, Sang-rok Hah
  • Publication number: 20020086509
    Abstract: A method of fabricating a contact pad of a semiconductor device is disclosed. The method includes forming a stopping layer over the semiconductor substrate. An interdielectric layer is formed over the stopping layer, and the interdielectric layer is planarized to expose at least a gate upper dielectric layer by using a material which exhibits a high-polishing selectivity with respect to the interdielectric layer. The interdielectric layer is etched in a region in which a contact pad will be formed on the semiconductor substrate. A conductive material is deposited on the semiconductor substrate. Finally, planarizing is carried out using a material which exhibits a high-polishing selectivity of the upper dielectric layer with respect to the conductive material.
    Type: Application
    Filed: November 8, 2001
    Publication date: July 4, 2002
    Inventors: Young-Rae Park, Jung-yup Kim, Bo-un Yoon, Sang-rok Hah
  • Publication number: 20020064955
    Abstract: A chemical mechanical polishing slurry includes an additive of a quaternary ammonium compound having a form of {N-(R1R2R3R4)}+X−, in which R1, R2, R3, and R4 are radicals, and X−is an anion derivative including halogen elements. Preferably, the quaternary ammonium compound is one of [(CH3)3NCH2CH2OH]Cl, [(CH3)3NCH2CH2OH]l, [(CH3)3NCH2CH20H]Br, [(CH3)3NCH2CH2H]CO3, and mixtures thereof. The slurry may further include a pH control agent formed of a base such as KOH, NH4OH, and (CH3)4NOH, and an acid such as HCI, H2SO4, H3PO4, and HNO3. Also, the pH control agent can include [(CH3)3NCH2CH2OH]OH. The slurry may further include a surfactant such as cetyldimethyl ammonium bromide, cetyldimethyl ammonium bromide, polyethylene oxide, polyethylene alcohol or polyethylene glycol.
    Type: Application
    Filed: October 16, 2001
    Publication date: May 30, 2002
    Inventors: Jae-dong Lee, Jong-won Lee, Bo-un Yoon, Sang-rok Hah
  • Publication number: 20020061635
    Abstract: A solution used for chemical mechanical polishing of a copper metal interconnection layer and a method of manufacturing a copper metal interconnection layer using the solution are provided. The method of manufacturing the copper metal interconnection layer includes the steps of forming a barrier layer along a stepped portion over the surface of the interdielectric layer having a recessed region; forming a copper seed layer along a stepped portion on the barrier layer, and exposing the barrier layer until exposing the surface of the interdielectric layer by chemical mechanical polishing using the solution including an oxidizing agent, a pH controlling agent, a chelate reagent, and deionized water. The oxidizing agent is hydrogen peroxide (H2O2), an oxidizing agent of a ferric series, or an oxidizing agent of an ammonium series. The pH controlling agent is an acidic or a basic solution.
    Type: Application
    Filed: July 5, 2001
    Publication date: May 23, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong-won Lee, Bo-Un Yoon, Sang-rok Hah
  • Publication number: 20020058460
    Abstract: A method of controlling a wafer polishing time using a sample-skip algorithm and a method of polishing a wafer using the same are provided. According to the method of controlling a wafer polishing time, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time &Dgr;t(n), to calculate the amount removed &Dgr;ToxP(n) from a polished layer on the wafer. The removal rate RRb(n) of a layer on a blanket wafer is calculated from the amount removed &Dgr;ToxP(n). A CMP time &Dgr;t(n+1) is determined for wafers of an n+1-th lot using the relationship equation &Dgr;t(n+1)={&Dgr;ToxT(n+1)+A}/RRb(n) where “A” is a constant and &Dgr;ToxT(n+1) is the target amount of a layer to be removed from a wafer of an n+1-th lot.
    Type: Application
    Filed: September 14, 2001
    Publication date: May 16, 2002
    Inventors: Jae-dong Lee, Bo-Un Yoon, Kyoung-Mo Yang, Sang-Rok Hah
  • Publication number: 20020052085
    Abstract: A gate electrode conductive layer is formed on an active region that is recessed relative to field oxide layers so as to define a damascene structure. The gate electrode conductive layer is formed on the active region but is not formed on a field region so that the thickness of an interlayer insulation layer deposited in a succeeding process is reduced, thereby reducing or preventing voids within the interlayer insulation layer. A polysilicon is formed on the bottom of the active region by selective epitaxial growth, thereby minimizing the influence of micro scratches, pits or stringers occurring on the bottom of the active region.
    Type: Application
    Filed: March 14, 2001
    Publication date: May 2, 2002
    Inventors: Hong-Kyu Hwang, Young-Rae Park, Jung-Yup Kim, Jeong-Sic Jeon, Bo-Un Yoon, Sang-Rok Hah
  • Publication number: 20020045337
    Abstract: An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.
    Type: Application
    Filed: July 27, 2001
    Publication date: April 18, 2002
    Inventors: Gee-won Nam, Gi-jong Park, Hong-kyu Hwang, Jun-shik Bae, Young-rae Park, Jung-yup Kim, Bo-un Yoon, Sang-rok Hah
  • Publication number: 20020034875
    Abstract: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.
    Type: Application
    Filed: May 21, 2001
    Publication date: March 21, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-rae Park, Jung-yup Kim, Bo-un Yoon, Kwang-bok Kim, Jae-phil Boo, Jong-won Lee, Sang-rok Hah, Kyung-hyun Kim, Chang-ki Hong
  • Publication number: 20020019128
    Abstract: A slurry for use in chemical mechanical polishing (CMP) of a metal layer. The CMP slurry includes an abrasive, a plurality of oxidizing agents, a stabilizer including an organic acid having a carboxyl group, a corrosion inhibitor which suppresses corrosion of a metal, a fluorine compound which reduces a difference in removal rates of a metal layer and a barrier layer, and deionized water. The plurality of oxidizing agents include a second oxidizing agent which oxidizes the metal and a first oxidizing agent which restores an oxidizing ability of the second oxidizing agent.
    Type: Application
    Filed: March 26, 2001
    Publication date: February 14, 2002
    Inventors: Jong-Won Lee, Bo-Un Yoon, Sang-Rok Hah
  • Patent number: 6335287
    Abstract: To form isolation trenches on a semiconductor substrate, chemical mechanical polishing (CMP) stopping patterns are formed on the substrate, and the substrate is then etched using the CMP stopping patterns as a mask. Then an insulating material is deposited to fill the trenches and cover the CMP stopping patterns. The insulating material is etched using a CMP process until the CMP stopping patterns become exposed, and is then etched using a wet or dry etching process. The wet or dry etching is continued until protruding insulating material above a surface of the substrate is a predetermined thickness, which corresponds to an amount of the insulating material that is etched during removal of the CMP stopping patterns and during intermediate processes prior to formation of a gate oxide layer.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: January 1, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-kyu Hwang, Bo-un Yoon, Kyu-hwan Chang, Sang-rok Hah
  • Patent number: 6218291
    Abstract: A method for forming contact plugs and simultaneously planarizing a substrate surface in an integrated circuit. Initially, a conductive structure is formed on a semiconductor substrate having a plurality of diffusion regions therein. A first insulating layer is formed over the semiconductor substrate including the conductive structure. The first insulating layer is etched using a contact hole forming mask to form a contact hole. A conductive layer is formed on the first insulating layer filling up the contact hole with the conductive layer. The conductive layer is etched until an upper surface of the first insulating layer is exposed. A second insulating layer is formed over the first insulating layer. A contact plug free of voids is formed and simultaneously a substrate surface is planarized by planarization-etching the second and first insulating layers.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: April 17, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Un Yoon, Seok-Ji Hong
  • Patent number: 6121146
    Abstract: A method for forming contact plugs of a semiconductor device includes a step of forming a conductive layer on an insulating layer filling up a contact hole. The method further comprises a step of planarization-etching an upper surface of the insulating layer as well as the contact plugs, after formation of the contact plugs by etching the conductive layer using an etch-back or a CMP process until at least the upper surface of the insulating layer is exposed. Alternatively, the conductive and insulating layers are simultaneously planarization-etched using a CMP process once to form the contact plugs and planarize the upper surface of the insulating layer. With this method, a bridge between interconnections which can be generated due to a scratch of the upper surface of the insulating layer can be prevented by planarization-etching the conductive layer after filling up a contact hole with the conductive layer.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: September 19, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Un Yoon, In-Kwon Jeong, Won-Seong Lee
  • Patent number: 6117766
    Abstract: A method of forming contact plugs in a semiconductor device employing multiple steps of a selective polishing technique is provided. This method selectively removes an interlayer insulating film and a conductive layer, thereby providing layers polished with a CMP process improved planarity and uniformity. The method includes forming an interlayer insulating film over a semiconductor substrate having a plurality of diffusion regions and conductive layers. The interlayer insulating film has an uneven upper surface as deposited, following the contours produced by underlying structures formed on the semiconductor substrate. A contact hole is opened through the interlayer insulating film to expose an upper surface of a conductive layer or a semiconductor substrate in the first region. A second conductive layer is deposited over the resulting structure. The key step of the present invention is then accomplished by performing a plurality of selective polishing steps on the resulting structure.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: September 12, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bo-Un Yoon, In-Kwon Jeong