Abstract: Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.

Abstract: A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.

Abstract: Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.

Abstract: In a method of chemically and mechanically polishing a layer, a substrate on which the layer having stepped portions is formed is prepared. The layer is primarily chemically and mechanically polished at a temperature of about 30° C. to about 80° C. to remove the stepped portions of the layer. The layer is secondarily chemically and mechanically polished without the stepped portions at a temperature of about 5° C. to about 25° C. to form a flat layer having a desired thickness. Thus, the stepped portions may be rapidly removed in an initial period so that the method may have an improved throughput.

Abstract: A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process.

Abstract: A method of manufacturing a stack-type semiconductor device, in which a first substrate and a second substrate are prepared so that the first substrate has a surface layer and the second substrate has an insulation layer. The first substrate and the second substrate are attached to each other to allow the surface layer to make contact with the insulation layer. The first substrate is partially separated from the second substrate to allow the surface layer to remain on a central portion of the second substrate. A sacrificial layer pattern is then formed on an edge portion of the second substrate having the surface layer. The sacrificial layer pattern and the surface layer are planarized. Thus, the sacrificial layer pattern may reduce damage to the edge portion of the second substrate so that the second substrate may have an improved flatness.

Abstract: In a method of recycling a substrate having an edge portion on which a stepped portion is formed, the substrate is chemically mechanically polished using a first slurry composition including fumed silica to remove the stepped portion. The substrate is then chemically mechanically polished using a second slurry composition including colloidal silica to improve the surface roughness of the substrate. The substrate having the edge region on which the stepped portion is formed may include a donor substrate used for manufacturing a silicon-on-insulator (SOI) substrate.

Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.

Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures.

Abstract: A polishing slurry, including an oxidizer, a corrosion inhibitor, and a polishing rate enhancer, wherein the polishing rate enhancer is a heterocyclic compound having at least one nitrogen in the ring, and the nitrogen is not directly bonded to a hydrogen atom which is mostly dissociated in the slurry.

Abstract: A test pattern and a method of controlling a CMP using the same are provided. The test pattern is disposed on a monitoring region of a semiconductor substrate having a main region and a monitoring region. The test pattern includes a planar region and a pattern region. The method comprises setting a correlation between a step difference of a test pattern and an etched thickness of a main pattern, then applying the CMP to a semiconductor substrate having the test pattern and the main pattern for a predetermined time. The step difference of the test pattern is measured and the etched thickness of the main pattern, which corresponds to the step difference of the test pattern, is determined from the correlation. A polishing time is corrected by comparing the determined etched thickness of the main pattern with a reference value, and the corrected polishing time is applied to a subsequent lot or subsequent substrate.

Abstract: Example embodiments are directed to a method of planarizing a semiconductor device. A first CMP process may be performed on an insulating layer to remove a stepped structure of the insulating layer. A second CMP process may be performed to planarize the insulating layer with the stepped structure removed until a given pattern is exposed. A process temperature of the first CMP process may be higher than that of the second CMP process. Accordingly, an initial stepped structure may be more readily removed in a planarization process of a surface of the semiconductor device, which may reduce the CMP process time and may increase the degree of planarization.

Abstract: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.

Abstract: Disclosed is a slurry and method for chemical-mechanical polishing operation. The slurry may contain abrasive particles, an oxidizer, a pH controller, a chelating agent and water. The viscosity of the slurry may be in the range of about 1.0 cP—about 1.05 cP, so that the step difference may be reduced between regions with patterns and without patterns even after completing the chemical-mechanical polishing operation. A permissible rate of depth of focus (DOF) may not need to be controlled in the subsequent photolithography operation, which may enable the subsequent photolithography operation to be conducted by an optical system with relatively low DOF.

Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.

Abstract: A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

Abstract: A multi-level transistor comprising a second active region having a single-crystalline characteristic and a method for manufacturing the multi-level transistor are disclosed. The multi-level transistor comprises a substrate comprising a first active region, a first transistor formed on the first active region, a first insulating layer covering the first transistor, and adapted to isolate the first active region, a second active region comprising a patterned first selective epitaxial growth (SEG) layer formed on the first insulating layer, and a second transistor formed on the second active region.

Abstract: A polishing slurry including an abrasive, deionized water, a pH controlling agent, and polyethylene imine, can control the removal rates of a silicon oxide layer and a silicon nitride layer which are simultaneously exposed during chemical mechanical polishing (CMP) of a conductive layer. A relative ratio of the removal rate of the silicon oxide layer to that of the silicon nitride layer can be controlled by controlling an amount of the choline derivative.

Abstract: In one aspect, a chemical-mechanical-polishing (CMP) slurry composition is provided which includes ceria abrasive contained in a solution, where the solution includes a viscosity increasing agent which includes a non-ionic polymer compound, and where a viscosity of the composition is at least 1.5 cP. In other aspects, the viscosity increasing agent includes one or more of poly(ethyleneglycol), a Gum compound and isopropyl alcohol.