Patents by Inventor Bo-un Yoon

Bo-un Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110039480
    Abstract: A polishing pad may include a base and a plurality of polishing protrusions on a surface of the base. Each polishing protrusion may include a sidewall defining an opening in a surface of the polishing protrusion opposite the base. In addition, portions of the sidewall opposite the base may define a contact surface.
    Type: Application
    Filed: August 12, 2010
    Publication date: February 17, 2011
    Inventors: Jae-Kwang Choi, Bo-Un Yoon, Myung-Ki Hong
  • Patent number: 7846801
    Abstract: Disclosed is a method of fabricating a semiconductor device including a multi-gate transistor. The method of fabricating a semiconductor device includes providing a semiconductor device having a number of active patterns which extend in a first direction, are separated by an isolation layer, and covered with a first insulating layer; forming a first groove by etching the isolation layer located between the active patterns adjacent to each other in the first direction; burying the first groove with a passivation layer; forming a second groove exposing at least a portion of both sides of the active patterns by etching the isolation layer located between the active patterns in a second direction intersecting the first direction; removing the passivation layer in the first groove; and forming a gate line filling at least a portion of the second groove and extending in the second direction.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: December 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-jun Kim, Seong-kyu Yun, Chang-ki Hong, Bo-un Yoon, Jong-won Lee, Ho-young Kim
  • Publication number: 20100267225
    Abstract: A method of manufacturing a semiconductor device, the method including forming a photoresist film on a substrate, and removing the photoresist film from the substrate using a composition that includes a sulfuric acid solution, a hydrogen peroxide solution, and a corrosion inhibitor.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Inventors: Hyo-san Lee, Bo-un Yoon, Kun-tack Lee, Dae-hyuk Kang, Jeong-nam Han, Jung-jae Myung, Hyung-pyo Hong, Hun-pyo Hong
  • Patent number: 7781330
    Abstract: Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chae-Iyoung Kim, Chang-ki Hong, Bo-un Yoon, Sung-ho Shin, Byoung-ho Kwon
  • Patent number: 7781281
    Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Young Kim, Chang-Ki Hong, Bo-Un Yoon, Joon-Sang Park
  • Publication number: 20100124817
    Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.
    Type: Application
    Filed: January 27, 2010
    Publication date: May 20, 2010
    Inventors: Ho-Young KIM, Chang-Ki HONG, Bo-Un YOON, Joon-Sang PARK
  • Patent number: 7678625
    Abstract: A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: March 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Heun Lim, Chang-Ki Hong, Bo-Un Yoon, Seong-Kyu Yun, Suk-Hun Choi, Sang-Yeob Han
  • Publication number: 20100062548
    Abstract: A photo key has a plurality of first regions spaced apart from one another on a semiconductor substrate, and a second region surrounding the first regions, and one of the first regions and the second region constitutes a plurality of photo key regions spaced apart from one another. Each of the photo key regions includes a plurality of first conductive patterns spaced apart from one another; and a plurality of second conductive patterns interposed between the first conductive patterns.
    Type: Application
    Filed: June 1, 2009
    Publication date: March 11, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoung-ho Kwon, Chang-ki Hong, Bo-un Yoon, Jae-dong Lee, Sang-jin Kim
  • Patent number: 7675175
    Abstract: A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. An upper layer barrier layer made from a conductive barrier material film is formed on an interlayer insulating film groove sidewall of the semiconductor device. Embedded in the groove is an upper layer seal ring wiring line with thickness of approximately 10 micrometers for instance, in which a plurality of isolated pockets of insulators are disbursed. These isolated pockets of insulators are formed using the interlayer insulating film which forms the damascene wiring line. Additionally, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in an element forming region, and an upper layer barrier layer is formed on the outside perimeter. The upper layer seal ring wiring line and both upper layer wiring lines all have damascene wiring structures.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: March 9, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Shunichi Tokitoh, Seiichi Kondou, Bo Un Yoon
  • Patent number: 7670942
    Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.
    Type: Grant
    Filed: September 23, 2006
    Date of Patent: March 2, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Young Kim, Chang-Ki Hong, Bo-Un Yoon, Joon-Sang Park
  • Publication number: 20100015729
    Abstract: In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.
    Type: Application
    Filed: July 15, 2009
    Publication date: January 21, 2010
    Inventors: Suk-Hun Choi, Jong-Won Lee, Chang-Ki Hong, Bo-Un Yoon
  • Publication number: 20090159952
    Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures.
    Type: Application
    Filed: March 4, 2009
    Publication date: June 25, 2009
    Inventors: Byoung-ho KWON, Chang-ki Hong, Bo-un Yoon, Jun-yong Kim
  • Publication number: 20090155991
    Abstract: A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
    Type: Application
    Filed: November 13, 2008
    Publication date: June 18, 2009
    Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Bo-Un Yoon, Jae-Dong Lee
  • Patent number: 7535052
    Abstract: A method of fabricating a non-volatile memory integrated circuit device and a non-volatile memory integrated circuit device fabricated by using the method are provided. A device isolation region is formed in a substrate to define a cell array region and a peripheral circuit region. A plurality of first and second pre-stacked gate structures is formed in the cell array region, and each has a structure in which a lower structure, a conductive pattern and a first sacrificial layer pattern are stacked. Junction regions are formed in the cell array region. Spacers are formed on side walls of the first and second pre-stacked gate structures. A second sacrificial layer pattern filling each space between the second pre-stacked gate structures is formed. The first sacrificial layer pattern is removed from each of the first and second pre-stacked gate structures.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: May 19, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-ho Kwon, Chang-ki Hong, Bo-un Yoon, Jun-yong Kim
  • Publication number: 20090121296
    Abstract: In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 14, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Byoung-ho Kwon, Sang-youn Jo, Jin-sook Choi, Chang-ki Hong, Bo-un Yoon, Hong-soo Kim, Se-rah Yun
  • Patent number: 7531456
    Abstract: Mask patterns used for forming patterns or trenches may include first mask patterns, which may be formed by a typical photolithography process, and second mask patterns, which may be formed in a self-aligned manner between adjacent first mask patterns. A sacrificial layer may be deposited and planarized such that the tops of the first mask patterns and the second mask patterns have planar surfaces. After the planarization of the sacrificial layer, the remaining the sacrificial layer may be removed by an ashing process.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Ho Kwon, Se-Rah Yun, Chang-Ki Hong, Bo-Un Yoon, Jae-Kwang Choi, Joon-Sang Park
  • Patent number: 7524757
    Abstract: A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: April 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-jun Kim, Chang-ki Hong, Bo-un Yoon, Jae-kwang Choi
  • Publication number: 20090098804
    Abstract: A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.
    Type: Application
    Filed: October 15, 2008
    Publication date: April 16, 2009
    Inventors: Jong-Heun Lim, Sung-Ho Shin, Bo-Un Yoon, Chang-Ki Hong
  • Publication number: 20090001051
    Abstract: A slurry composition for polishing metal includes a polymeric polishing accelerating agent, the polymeric polishing accelerating agent including a backbone of hydrocarbon and a side substituent having at least one of a sulfonate ion (SO3?) and a sulfate ion (OSO3?), and an acidic aqueous solution.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Inventors: Jong-Won Lee, Sang-Yeob Han, Chang-Ki Hong, Bo-Un Yoon, Jae-Dong Lee
  • Publication number: 20080247219
    Abstract: A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions of the first metal pattern may be between the substrate and the first insulating layer, and the first insulating layer may have a first opening therein exposing a portion of the first metal pattern. The electrode may be in the opening with the electrode being electrically coupled with the exposed portion of the first metal pattern. The first insulating layer may be between the second insulating layer and the substrate, and the second insulating layer may have a second opening therein exposing a portion of the electrode.
    Type: Application
    Filed: April 3, 2008
    Publication date: October 9, 2008
    Inventors: Suk-Hun Choi, In-Gyu Baek, Seong-Kyu Yun, Jong-Heun Lim, Chagn-Ki Hong, Bo-Un Yoon