Patents by Inventor Bo-Young Seo
Bo-Young Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7408230Abstract: Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.Type: GrantFiled: March 23, 2005Date of Patent: August 5, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon Park, Sung-Taeg Kang, Seong-Gyun Kim, Bo-Young Seo, Sung-Woo Park
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Publication number: 20080137417Abstract: A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gatesare connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.Type: ApplicationFiled: January 21, 2008Publication date: June 12, 2008Inventors: BO-YOUNG SEO, Hee-Seog Jeon, Sung-Taeg Kang
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Publication number: 20080130367Abstract: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.Type: ApplicationFiled: February 7, 2008Publication date: June 5, 2008Inventors: Sung-Taeg Kang, Hee-Seog Jeon, Jeong-Uk Han, Chang-Hun Lee, Bo-Young Seo, Chang-Min Jeon, Eun-Mi Hong
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Publication number: 20080089136Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.Type: ApplicationFiled: October 11, 2007Publication date: April 17, 2008Inventors: Hyun-Khe Yoo, Jeong-Uk Han, Hee-Seog Jeon, Sung-Gon Choi, Bo-Young Seo, Chang-Min Jeon, Ji-Do Ryu
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Publication number: 20080076242Abstract: A method of fabricating a nonvolatile memory device includes preparing a semiconductor substrate having a cell array region and a peripheral circuit region. Cell gate patterns are formed in the cell array region, and peripheral gate patterns are formed in the peripheral circuit region. Each of the cell gate patterns includes a control gate pattern and a capping pattern, and each of the peripheral gate patterns has a smaller thickness than the cell gate pattern. An interlayer dielectric layer is formed on the resultant structure having the cell gate patterns and the peripheral gate patterns. The interlayer dielectric layer is planarized by etching until the top surface of the capping pattern is exposed, so that an interlayer dielectric pattern is formed. The interlayer dielectric pattern covers the peripheral circuit region and fills a space between the cell gate patterns.Type: ApplicationFiled: August 14, 2007Publication date: March 27, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-Gon Choi, Hyun-Khe Yoo, Bo-Young Seo, Chang-Min Jeon, Ji-Do Ryu
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Patent number: 7339232Abstract: A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.Type: GrantFiled: October 21, 2005Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-Young Seo, Hee-Seog Jeon, Sung-Taeg Kang
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Patent number: 7320913Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.Type: GrantFiled: March 3, 2006Date of Patent: January 22, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Taeg Kang, Hyok-Ki Kwon, Bo Young Seo, Seung Beom Yoon, Hee Seog Jeon, Yong-Suk Choi, Jeong-Uk Han
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Publication number: 20080012062Abstract: An electrically erasable programmable read-only memory (EEPROM) device includes an EEPROM cell located on a semiconductor substrate, the EEPROM cell including a memory transistor and a selection transistor. A source region and a drain region are located on the semiconductor substrate adjacent to opposite sides of the EEPROM cell, respectively, and a floating region is positioned between the memory transistor and the selection transistor. The source region includes a first doped region, a second doped region and a third doped region, where the first doped region surrounds a bottom surface and sidewalls of the second doped region, and the second doped surrounds a bottom surface and sidewalls of the third doped region. Also, a second impurity concentration of the second doped region is higher than that of the first doped region and lower than that of the third doped region.Type: ApplicationFiled: July 11, 2007Publication date: January 17, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Khe YOO, Jeong-Uk HAN, Hee-Seog JEON, Sung-Gon CHOI, Bo-young SEO, Chang-Min JEON, Ji-Do RYU
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Publication number: 20080008003Abstract: A non-volatile memory device includes a memory cell block, a first switching block, and a second switching block. A plurality of memory cells are arranged in the memory cell block and each of the memory cells includes a memory transistor having a floating gate and a control gate and is connected to a local bit line and includes a selection transistor connected to the memory transistor in series that is connected to a source line. The first switching block selectively connects a global bit line to the local bit line and the second switching block controls the memory cells in the memory cell block in units of a predetermined number of bits. The first switching block includes at least two switching devices connected in parallel between the global bit line and the local bit line.Type: ApplicationFiled: April 23, 2007Publication date: January 10, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun-Khe Yoo, Ji-Do Ryu, Bo-Young Seo, Chang-Min Jeon, Hee-Seog Jeon, Sung-Gon Choi, Jeong-Uk Han
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Patent number: 7285820Abstract: A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.Type: GrantFiled: August 31, 2005Date of Patent: October 23, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hoon Park, Seung-Beom Yoon, Jeong-Uk Han, Seong-Gyun Kim, Sung-Taeg Kang, Bo-Young Seo, Sang-Woo Kang, Sung-Woo Park
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Publication number: 20070195595Abstract: A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to a corresponding one of the pair of memory transistors, and the other bit line being connected to a corresponding other of the pair of memory transistors.Type: ApplicationFiled: November 16, 2006Publication date: August 23, 2007Inventors: Bo-Young Seo, Hee-Seog Jeon, Jeong-Uk Han, Sung-Taeg Kang
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Publication number: 20070091682Abstract: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.Type: ApplicationFiled: June 28, 2006Publication date: April 26, 2007Inventors: Sung-Taeg Kang, Hee-Seog Jeon, Jeong-Uk Han, Chang-Hun Lee, Bo-Young Seo, Chang-Min Jeon, Eun-Mi Hong
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Patent number: 7190024Abstract: In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range.Type: GrantFiled: January 10, 2006Date of Patent: March 13, 2007Assignee: Samsung Electronics, Co., Ltd.Inventors: Sung-Taeg Kang, Jeong-Uk Han, Sung-Woo Park, Seung-Beom Yoon, Ji-Hoon Park, Bo-Young Seo
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Publication number: 20070045673Abstract: A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.Type: ApplicationFiled: July 18, 2006Publication date: March 1, 2007Inventors: Hee-Seog Jeon, Jeong-Uk Han, Chang-Hun Lee, Sung-Taeg Kang, Bo-Young Seo, Hyok-Ki Kwon
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Publication number: 20060108610Abstract: In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range.Type: ApplicationFiled: January 10, 2006Publication date: May 25, 2006Inventors: Sung-Taeg Kang, Jeong-Uk Han, Sung-Woo Park, Seung-Beom Yoon, Ji-Hoon Park, Bo-Young Seo
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Patent number: 7041557Abstract: In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range.Type: GrantFiled: April 27, 2004Date of Patent: May 9, 2006Assignee: Samsung Electronics, Co., Ltd.Inventors: Sung-Taeg Kang, Jeong-Uk Han, Sung-Woo Park, Seung-Beom Yoon, Ji-Hoon Park, Bo-Young Seo
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Publication number: 20060092705Abstract: A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.Type: ApplicationFiled: October 21, 2005Publication date: May 4, 2006Inventors: Bo-Young Seo, Hee-Seog Jeon, Sung-Taeg Kang
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Publication number: 20060044915Abstract: A flash memory device according to the present invention includes a semiconductor fin including a top surface and a side surface originated from different crystal planes. The flash memory device comprises: insulating layers having different thicknesses formed on a side surface and a top surface of the semiconductor fin, a storage electrode, a gate insulating layer and a control gate electrode sequentially formed on the insulating layers. A thin insulating layer enables charges to be injected or emitted through it, and a thick insulating layer increases a coupling ratio. Accordingly, it is possible to increase an efficiency of a programming or an erase operation of a flash memory device.Type: ApplicationFiled: August 31, 2005Publication date: March 2, 2006Inventors: Ji-Hoon Park, Seung-Beom Yoon, Jeong-Uk Han, Seong-Gyun Kim, Sung-Taeg Kang, Bo-Young Seo, Sang-Woo Kang, Sung-Woo Park
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Publication number: 20060006452Abstract: Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.Type: ApplicationFiled: March 23, 2005Publication date: January 12, 2006Inventors: Ji-Hoon Park, Sung-Taeg Kang, Seong-Gyun Kim, Bo-Young Seo, Sung-Woo Park
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Publication number: 20050106897Abstract: In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range.Type: ApplicationFiled: April 27, 2004Publication date: May 19, 2005Inventors: Sung-Taeg Kang, Jeong-Uk Han, Sung-Woo Park, Seung-Beom Yoon, Ji-Hoon Park, Bo-Young Seo