Abstract: A method for rate adaptation in a communication device includes, during a time interval, transmitting over a wireless channel to a peer communication device both (i) communication packets that carry user data, at a communication data rate, and (ii) channel-probing packets for probing channel conditions, at a channel-probing data rate that is derived from the communication data rate. A first statistical performance of the communication packets, and a second statistical performance of the channel-probing packets, are estimated over the time interval. The communication data rate is set for a subsequent time interval based on at least one of the first statistical performance and the second statistical performance.

Abstract: Systems and methods are provided for interpreting traffic information. In one embodiment, a method includes: receiving, by a processor, visual data from a plurality of vehicles, wherein the visual data is associated with an intersection of a roadway having one or more lanes; receiving, by the processor, vehicle data from the plurality of vehicles, wherein the vehicle data is associated with the intersection of the roadway; determining, by the processor, a first state of a traffic light associated with the intersection based on the visual data; determining, by the processor, a second state of the traffic light associated with the intersection based on the vehicle data; correlating, by the processor, the first state and the second state based on a time synchronization; assigning, by the processor, the traffic light to a lane of the roadway based on the correlating; and communicating, by the processor, the traffic light to lane assignment for use in controlling a vehicle of the multiple vehicles.

Abstract: It is an object of the present disclosure to provide a formulation for injectable and topical collagenase, which will have extended residence time for the drug at the therapeutic targeted area for the indication being treated. It is a further object of the disclosure to provide a slow release formulation for collagenase, which is compatible with the active ingredient and does not adversely affect its activity. Still a further object of the disclosure is to provide an injectable formulation for collagenase which can be effectively administered to a patient with a small size needle without exhibiting pre-gelation, which would interfere with the ability to deliver the required dose for treatment. Still a further object of the disclosure is to provide a water-based topical formulation for collagenase which will be more compatible with other topically used medications to achieve better results.

Abstract: An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: The present disclosure relates to methods and associated systems for managing a plurality of device-exchange stations. The method includes, for example, (1) determining a score for each of the plurality of device-exchange stations based on an availability of energy storage devices positioned in each of the device-exchange stations; (2) determining a sequence of the plurality of device-exchange stations based on the score of each of the device-exchange stations; and (3) determining a price rate for each of the device-exchange stations by mapping the sequence of the device-exchange stations to a characteristic curve corresponding to a distribution of the price rate.

Abstract: A heat dissipation substrate includes a substrate, a heat conducting element, an insulating filling material, a first circuit layer, and a second circuit layer. The substrate has a first surface, a second surface opposite the first surface, and a through groove communicating the first surface with the second surface. The heat conducting element is disposed in the through groove. The heat conducting element includes an insulating material layer and at least one metal layer. The insulating filling material is filled in the through groove for fixing the heat conducting element into the through groove. The first circuit layer is disposed on the first surface of the substrate and exposes a portion of the heat conducting element. The second circuit layer is disposed on the second surface of the substrate. The first circuit layer and the metal layer are respectively disposed on two opposite sides of the insulating material layer.

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

Abstract: The present invention provides a method for producing a drug product comprising a combination of highly purified collagenase I and collagenase II from Clostridium histolyticum. The method utilizes an improved medium for the cultivation of Clostridium histolyticum which includes a non-meat-derived (i.e., non-mammalian) peptone or vegetable peptone. The method includes one or more of: (1) reducing glucose content in the meat-free or vegetable-derived media; and (2) increasing the salt concentration in the meat-free or vegetable-derived media. Also provided is a drug product which includes collagenase I and collagenase II at an optimized fixed mass ratio, and which has a purity of greater than at least 95%.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.

Abstract: The present disclosure relates to methods and associated systems for managing a plurality of device-exchange stations. The method includes, for example, (1) receiving empirical information regarding exchanges of energy storage devices from each of the plurality of device-exchange stations in an initial time period; (2) determining a target time period; (3) identifying a plurality of reference factors and associated weighting values based on empirical information regarding exchanges of energy storage devices; (4) determining demand information during the target time period for each of the plurality of device-exchange stations during the target time period for each of the device-exchange stations; and (5) forming a plurality of charging plans for each of the plurality of device-exchange stations according to demand information during the target time period.

Abstract: Disclosed herein is a deep learning model that can be used for performing speech or image processing tasks. The model uses multi-task training, where the model is trained for at least two inter-related tasks. For face detection, the first task is face detection (i.e. face or non-face) and the second task is facial feature identification (i.e. mouth, eyes, nose). The multi-task model improves the accuracy of the task over single-task models.

Abstract: A device may include a semiconductor-on-insulator (SOI) structure that may include a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer. The semiconductor layer may include a first conductivity region and a second conductivity region at least partially arranged within the semiconductor layer. The device may further include a gate structure arranged over the semiconductor layer and between the first conductivity region and the second conductivity region; a first conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; a second conductor element arranged to electrically contact the gate structure; and a conducting member connecting the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: The present disclosure relates to anti-CD40 antibodies, such as humanized anti-CD40 antibodies, that may be used in various therapeutic, prophylactic and diagnostic methods. The antibodies generally block the ability of CD40 to bind CD154 and do so without activating the cell expressing CD40 (e.g., a B cell). The present antibodies or fragments thereof may be used to reduce complications associated with organ or tissue transplantation.

Abstract: A dimming circuit for dimming a current flowing through a light emitting device, having: a multi-function pin, configured to receive a dimming signal; wherein when the dimming signal is an analog voltage signal, an amplitude of the current flowing through the light emitting device is regulated based on the dimming signal; when the dimming signal is a pulse signal and a frequency of the dimming signal is in a first frequency range, a duty cycle of the current flowing through the light emitting device is regulated based on the dimming signal; and when the dimming signal is the pulse signal and the frequency of the dimming signal is in a second frequency range, the amplitude of the current flowing through the light emitting device is regulated based on the dimming signal.

Abstract: A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.

Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.

Abstract: An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, and source/drain regions. The gate structure comprises an yttrium oxide layer over the semiconductor substrate, an aluminum oxide layer over the yttrium oxide layer, and a gate electrode on the aluminum oxide layer. The source/drain regions are on the semiconductor substrate and on opposite sides of the gate structure.