Abstract: A PLL circuit for generating a modulated carrier signal includes a digitally controlled oscillator (DCO) to generate the modulated signal. The PLL circuit receives a desired phase change as a modulation signal at each cycle of a non-uniform clock, derived from the a DCO output and a uniform reference clock. This phase change adjusts the DCO's frequency. The circuit also receives a frequency control word, representing the ratio of the desired carrier frequency to the reference clock frequency. The phase change and frequency control word are accumulated to predict the DCO's output phase. A non-uniform clock compensation circuit calculates a compensation value for the phase change. A phase detector estimates the error between the predicted phase and the time offset between the reference clock and DCO output, generating a control signal for the DCO based on this error.

Abstract: A PLL circuit for generating a modulated carrier signal includes a digitally controlled oscillator (DCO) to generate the modulated signal. The PLL circuit receives a desired phase change as a modulation signal at each cycle of a non-uniform clock, derived from the a DCO output and a uniform reference clock. This phase change adjusts the DCO's frequency. The circuit also receives a frequency control word, representing the ratio of the desired carrier frequency to the reference clock frequency. The phase change and frequency control word are accumulated to predict the DCO's output phase. A non-uniform clock compensation circuit calculates a compensation value for the phase change. A phase detector estimates the error between the predicted phase and the time offset between the reference clock and DCO output, generating a control signal for the DCO based on this error.

Abstract: The present disclosure relates to an amplifier circuit comprising a main amplifier circuit comprising a plurality of first switched-capacitor, SC, house-of-cards, HoC, amplifier cells coupled in parallel between an input and an output of the main amplifier circuit, at least one peak amplifier circuit comprising a plurality of second SC HoC amplifier cells coupled in parallel between an input and an output of the peak amplifier circuit, wherein the output of the main amplifier circuit and the output of the peak amplifier circuit are coupled to a common load.

Abstract: Examples relate to a circuit arrangement, a time-mode arithmetic unit circuit arrangement, an all-digital phase-locked loop, and corresponding methods. A circuit arrangement is configured to discard charges from a capacitive circuit element of the circuit arrangement based on a width of one or more signal pulses of an input signal being provided to the circuit arrangement, with the rate at which the charges are discarded being dependent on at least one control signal being provided to the circuit arrangement. The circuit arrangement is configured to provide an output signal flank having a delay relative to a readout signal flank being provided to the circuit arrangement, with the delay being based on the charges stored in the capacitive circuit element at the time the readout signal flank is provided to the circuit arrangement.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: An electronic circuit, such as a transmitter, for receiving a modulating signal including an in-phase component (I) and a quadrature component (Q). The electronic circuit has a first digital-to-RF-amplitude convertor (DRAC) receiving the in-phase component and a second digital-to-RF-amplitude convertor (DRAC) receiving the quadrature component. The first digital-to-RF-amplitude convertor is operative in a first duty cycle that is different from 50% and the second digital-to-RF-amplitude convertor is operative in a second duty cycle that is different from 50% and substantially the same in value as said first duty cycle.

Abstract: An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillators to perform sensitivity testing. Tile on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillator, to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: An on-chip receiver sensitivity test mechanism for use in an integrated RF transmitter wherein the transmitter and the receiver share the same oscillator. The mechanism obviates the need to use expensive RF signal generator test equipment with built-in modulation capability and instead permits the use of very low cost external RF test equipment. The invention utilizes circuitry already existing in the transceiver, namely the modulation circuitry and local oscillator, to perform sensitivity testing. The on-chip LO is used to generate the modulated test signal that otherwise would need to be provided by expensive external RF test equipment with modulation capability. The modulated LO signal is mixed with an externally generated unmodulated CW RF signal to generate a modulated signal at IF which is subsequently processed by the remainder of the receiver chain. The recovered data bits are compared using an on-chip BER meter or counter and a BER reading is generated.

Abstract: An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test.

Abstract: A sync detect circuit is comprised of two serial data registers (40) and (42), each for storing a single word. A plurality of current sources in current source banks (44) and (46) are operable to convert the bits in the stored sync word to a differential current domain. Depending upon the logic state, the currents are added on two lines (50) and (52). When the differential current falls below a predetermined limit, a frame sync signal is generated to latch the next and following words into a data latch (34). These are then transferred out to a system upon the generation of a system data clock.