Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.

Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Abstract: A novel and useful noise reduction technique that improves the noise figure (NF) of a common-source (CS) low noise amplifier (LNA). The technique exploits dc current reuse and increases transconductance of the CS transistor while maintaining its power consumption. By using noise reduction and dc current reuse techniques, the thermal current noise of the noise cancellation stage is reduced without adding any extra branch to the circuit. As a result, the current thermal noise of second stage decreases dramatically leading to better NF without consuming any extra power. Moreover, since the circuit block is implemented using a pMOS transistor, the second order nonlinearity of pMOS and nMOS transistors cancel each other, resulting in improved nonlinearity performance of the LNA, including improvements to both IIP2 and IIP3.

Abstract: Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.

Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.

Abstract: A novel and useful mm-wave frequency generation system is disclosed that takes advantage of injection locking techniques to generate an output oscillator signal with improved phase noise (PN) performance and power efficiency. Low frequency and high frequency DCOs as well as a pulse generator make up the oscillator system. A fundamental low frequency (e.g., 30 GHz) signal and its sufficiently strong higher (e.g., fifth) harmonic (e.g., 150 GHz) are generated simultaneously in a single oscillator system. The second high frequency DCO having normally poor phase noise is injected locked to the first low frequency DCO having good phase noise. Due to injection locking, the high frequency output signal generated by the second DCO exhibits good phase noise since the phase noise of the second DCO tracks that of the first DCO.

Abstract: An all-digital phase locked loop (ADPLL) receives an analog input supply voltage which is utilized to operate analog circuitry within the ADPLL. The ADPLL of the present disclosure scales this analog input supply voltage to provide a digital input supply voltage which is utilized to operate digital circuitry within the ADPLL. The analog circuitry includes a time-to-digital converter (TDC) to measure phase errors within the ADPLL. The TDC can be characterized as having a resolution of the TDC which is dependent, at least in part, upon the digital input supply voltage. In some situations, process, voltage, and/or temperature (PVT) variations within the ADPLL can cause the digital input supply voltage to fluctuate, which in turn, can cause fluctuations in the resolution of the TDC. These fluctuations in the resolution of the TDC can cause in-band phase noise of the ADPLL to vary across the PVT variations.

Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) Obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Abstract: A novel and useful high-order discrete-time charge rotating (CR) infinite impulse response (IIR) low pass filter is presented. The filter utilizes history capacitor arrays incorporating banks of capacitors. A linear interpolation technique is used in the IIR filter with second order antialiasing filtering, whose transfer function is sinc(x)2 per stage. It also uses a gm cell, rather than operational amplifiers, and is thus compatible with digital nanoscale technology. A 7th-order charge-sampling discrete time filter is disclosed. The order of the filter is easily extendable to higher orders. The charge rotating filter is process scalable with Moore's law and amenable to digital nanoscale CMOS technology. Bandwidth of the filter is precise and robust to PVT variation. The filter exhibits very low power consumption per filter pole, low input-referred noise, wide tuning range, excellent linearity and low area per minimum bandwidth and filter pole.

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Abstract: The invention relates to a radio frequency oscillator, the radio frequency oscillator comprising a resonator circuit being resonant at an excitation of the resonator circuit in a differential mode and at an excitation of the resonator circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at the excitation in the differential mode, and wherein the resonator circuit has a common mode resonance frequency at the excitation in the common mode, a first excitation circuit being configured to excite the resonator circuit in the differential mode to obtain a differential mode oscillator signal oscillating at the differential mode resonance frequency, and a second excitation circuit being configured to excite the resonator circuit in the common mode to obtain a common mode oscillator signal oscillating at the common mode resonance frequency.

Abstract: The invention relates to a resonator circuit, the resonator circuit comprising a transformer comprising a primary winding and a secondary winding, wherein the primary winding is inductively coupled with the secondary winding, a primary capacitor being connected to the primary winding, the primary capacitor and the primary winding forming a primary circuit, and a secondary capacitor being connected to the secondary winding, the secondary capacitor and the secondary winding forming a secondary circuit, wherein the resonator circuit has a common mode resonance frequency at an excitation of the primary circuit in a common mode, wherein the resonator circuit has a differential mode resonance frequency at an excitation of the primary circuit in a differential mode, and wherein the common mode resonance frequency is different from the differential mode resonance frequency.

Abstract: A frequency generator is disclosed. The frequency generator is for generating an oscillator clock according to a reference clock, and the frequency generator is used in a frequency hopping system that switches a carrier frequency among a plurality of channels, and the carrier frequency further carries a modulation frequency for data transmission. The frequency generator includes: a frequency hopping and modulation control unit, arranged for generating a current channel according to a channel hopping sequence and a frequency command word (FCW) based on the reference clock, a digital-controlled oscillator (DCO), arranged for to generating the oscillator clock according to an oscillator tuning word (OTW) obtained according to the estimated DCO normalization value. An associated method is also disclosed.

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

Abstract: Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.

Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.

Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

Abstract: Systems and methods for compensating a non-linearity of a digitally controlled oscillator (DCO) are presented. Data comprising a plurality of silicon measurements is received. Each silicon measurement in the plurality of silicon measurements is compared to an ideal value. Based on the comparing, a plurality of compensation vectors is generated. Each compensation vector comprises at least one silicon measurement. At least one frequency is adjusted based on a compensation vector in the plurality of compensation vectors. A digitally-controlled oscillator frequency is generated based on the adjusted at least one frequency.

Abstract: Systems and methods are provided for hopping a digitally controlled oscillator (DCO) among a plurality of channels, wherein a gain of the DCO KDCO is a nonlinear function of frequency. A first normalized tuning word (NTW) corresponding to a first channel of the plurality of channels is generated. A first normalizing gain multiplier X is generated based on the nonlinear function of frequency, on an estimate of the nonlinear function of frequency, at a first frequency corresponding to the first channel. The first NTW is multiplied by the first X to obtain a first oscillator tuning word (OTW). The first OTW is input to the DCO to cause the DCO to hop to the first channel. A system for hopping among a plurality of channels at a plurality of respective frequencies comprises a phase-locked loop (PLL), a digitally controlled oscillator (DCO), a multiplexer, and an arithmetic module.