Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first pad region located at a first region of the first semiconductor chip and a second pad region located at a second region of the first semiconductor chip. The second semiconductor chip has a third pad region located at a first region of the second semiconductor chip and a fourth pad region located at a second region of the second semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip to be offset in a first lateral direction relative to the first semiconductor chip.

Abstract: A semiconductor apparatus may include a logic circuit, a power gating circuit and a power gating control system. The logic circuit may operate by receiving a first power supply voltage and a second power supply voltage, and may retain an output signal at a predetermined logic value during a standby operation of the semiconductor apparatus. The power gating circuit may apply the first power supply voltage and the second power supply voltage to the logic circuit when a gating control signal is in an enabled state. The power gating control system may test whether the output signal of the logic circuit retains the predetermined logic value when the power gating circuit is turned off, and may generate the gating control signal based on a test result and an operation mode of the semiconductor apparatus.

Abstract: A semiconductor apparatus may include a logic circuit, a power gating circuit and a power gating control system. The logic circuit may operate by receiving a first power supply voltage and a second power supply voltage, and may retain an output signal at a predetermined logic value during a standby operation of the semiconductor apparatus. The power gating circuit may apply the first power supply voltage and the second power supply voltage to the logic circuit when a gating control signal is in an enabled state. The power gating control system may test whether the output signal of the logic circuit retains the predetermined logic value when the power gating circuit is turned off, and may generate the gating control signal based on a test result and an operation mode of the semiconductor apparatus.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a burn-in test signal, a clock signal and command/address signals. The semiconductor device enters a first test mode if the burn-in test signal is inputted. The semiconductor device enters a second test mode according to a level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the first test mode. The semiconductor device enters a third test mode according to an other level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the second test mode.

Abstract: A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

Abstract: The semiconductor device includes a command generator, an information signal storage unit, a termination signal generator and a code generator. The command generator generates a mode register write command signal, a start command signal and a termination command signal from external command signals. The information signal storage unit extracts information signals from the external command signals to store the information signals and output the information signals. The termination signal generator generates a termination signal in response to the information signals. The code generator generates code signals to control a timing of a control signal.

Abstract: Semiconductor chips are provided. The semiconductor chip includes a first data pad, a first data strobe pad and a second data pad sequentially arrayed from a command address pad in a first direction. In addition, the semiconductor chip includes a third data pad, a second data strobe pad and a fourth data pad sequentially arrayed from the command address pad in a second direction. Data are inputted and outputted through the first and fourth data pads or through the second and third data pads in a predetermined bit organization. Related semiconductor chip packages and semiconductor systems are also provided.

Abstract: A semiconductor device includes a flag signal generating circuit, a reference voltage generating circuit, and a first buffer. The flag signal generating circuit generates a flag signal based on an internal command and a training control code which are extracted from an external signal. The reference voltage generating circuit receives a set code based on the flag signal, an input control code and an output control code, and generates a reference voltage whose level is set based on the set code. The first buffer buffers the external signal based on the reference voltage to generate an internal signal, and generates a calibration code from the internal signal based on the flag signal to output the calibration code.

Abstract: A semiconductor device includes a flag signal generating circuit, a reference voltage generating circuit, and a first buffer. The flag signal generating circuit generates a flag signal based on an internal command and a training control code which are extracted from an external signal. The reference voltage generating circuit receives a set code based on the flag signal, an input control code and an output control code, and generates a reference voltage whose level is set based on the set code. The first buffer buffers the external signal based on the reference voltage to generate an internal signal, and generates a calibration code from the internal signal based on the flag signal to output the calibration code.

Abstract: The semiconductor device includes a command generator, an information signal storage unit, a termination signal generator and a code generator. The command generator generates a mode register write command signal, a start command signal and a termination command signal from external command signals. The information signal storage unit extracts information signals from the external command signals to store the information signals and output the information signals. The termination signal generator generates a termination signal in response to the information signals. The code generator generates code signals to control a timing of a control signal.

Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a burn-in test signal, a clock signal and command/address signals. The semiconductor device enters a first test mode if the burn-in test signal is inputted. The semiconductor device enters a second test mode according to a level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the first test mode. The semiconductor device enters a third test mode according to an other level combination of the command/address signals in synchronization with the clock signal after the semiconductor device enters the second test mode.

Abstract: Semiconductor systems are provided. A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a command and a power supply voltage. The second semiconductor device may generate pulses of a reset signal for an initialization operation and pulses of an auto-refresh signal for an auto-refresh operation in response to a first reset command generated in response to the command after the power supply voltage reaches a target voltage level. The second semiconductor device may generate the pulses of the reset signal in response to a second reset command generated in response to the command.

Abstract: The semiconductor device includes a flag signal generator, a reference voltage generator and a first buffer. The flag signal generator generates a flag signal in response to an internal command and an information code. The reference voltage generator receives a set code in response to the flag signal, and generates a reference voltage having a voltage level regulated according to the set code. The first buffer buffers the external signal in response to the reference voltage to generate an internal signal, and generates a calibration code in response to the flag signal.

Abstract: The semiconductor device includes a command generator, an information signal storage unit, a termination signal generator and a code generator. The command generator generates a mode register write command signal, a start command signal and a termination command signal from external command signals. The information signal storage unit extracts information signals from the external command signals to store the information signals and output the information signals. The termination signal generator generates a termination signal in response to the information signals. The code generator generates code signals to control a timing of a control signal.

Abstract: A semiconductor device includes a clock shifter configured to shift an active control signal by a predetermined number of clocks and output a shift signal according to a test signal; a command selection block configured to select any one of the active control signal and the shift signal according to the test signal, and output an active command signal; an active control block configured to control an active state of a bank active signal according to the active command signal; and an address latch block configured to latch an internal address according to the active command signal and the active control signal, and output a row address to a core region.