Abstract: A semiconductor system includes a controller configured to output a clock enable signal, first to third command/address signals, a chip select signal, first and second entry commands and an exit command, and receive an output signal; and a semiconductor device configured to latch the first and second command/address signals and transfer the output signal in response to the chip select signal and the first entry command, latch the first and third command/address signals and transfer the output signal in response to the chip select signal and the second entry command, and transfer data generated by the first to third command/address signals as the output signal in response to the clock enable signal and the exit command signal.

Abstract: A semiconductor system includes a controller configured to output a clock enable signal, first to third command/address signals, a chip select signal, first and second entry commands and an exit command, and receive an output signal; and a semiconductor device configured to latch the first and second command/address signals and transfer the output signal in response to the chip select signal and the first entry command, latch the first and third command/address signals and transfer the output signal in response to the chip select signal and the second entry command, and transfer data generated by the first to third command/address signals as the output signal in response to the clock enable signal and the exit command signal.

Abstract: A data strobe signal generation circuit includes: an enable signal generation unit configured to decode a test signal and generate an enable signal; an internal clock generation unit configured to generate a rising clock signal and a falling clock signal in response to the test signal; and a data strobe signal output unit configured to selectively buffer first and second powers in response to the rising clock signal and the falling clock signal, and output a data strobe signal.

Abstract: A semiconductor memory apparatus includes memory banks, each having sub banks. The semiconductor memory apparatus is configured to allocate same test input/output line to a certain sub bank of one memory bank and a certain sub bank of another memory bank during a multi-bit test.

Abstract: A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.

Abstract: A data buffer control circuit and a semiconductor memory apparatus including the same are presented. The data buffer control circuit may include an internal command signal generator and a buffer enable signal generator. The internal command signal generator is configured to generate an internal command signal that is activated if delayed command signals are conditioned in a predetermined state of level combination. The buffer enable signal generator is configured to generate a buffer enable signal, which enables a data buffer receiving data in a writing mode, from the internal command signal in sync with a falling edge of an internal clock signal.

Abstract: A semiconductor memory chip includes a first pad unit configured to receive a first data and a first strobe signal, and a first selection transfer unit configured to transfer the first data and the first strobe signal to a first write path circuit in a first mode, and transfer the first data and the first strobe signal to a second write path circuit in a swap mode.

Abstract: A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.

Abstract: A data strobe signal generation circuit includes: an enable signal generation unit configured to decode a test signal and generate an enable signal; an internal clock generation unit configured to generate a rising clock signal and a falling clock signal in response to the test signal; and a data strobe signal output unit configured to selectively buffer first and second powers in response to the rising clock signal and the falling clock signal, and output a data strobe signal.

Abstract: There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.

Abstract: There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.

Abstract: A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.

Abstract: Disclosed is a semiconductor integrated circuit that allows a fail path to be detected. A semiconductor integrated circuit as described herein can be configured to include a data register that can receive input data to generate and store a write expectation value and a read expectation value, during a period in which a test mode is activated, a first comparing unit that compares write data written in a memory cell with the write expectation value, and a second comparing unit that compares read data read from the memory cell with the read expectation value.

Abstract: The present invention relates to a semiconductor memory, and more specifically, to a data output circuit capable of differentiating global data lines in accordance to an operation mode to output them to a data input/output pin. The present invention includes: a multiplexer selecting any one of a plurality of global input/output lines which can receive variable data bandwidth directed by control signals and which can output data carried on the selected global input/output line, and a controller generating the control signals in accordance to operation mode signals corresponding to a data bandwidth and address signals provided for selecting data and providing them to the multiplexer. Thereby, the present invention can realize an improved data read speed by reducing the loading of the global input/output line.

Abstract: A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.

Abstract: A semiconductor memory apparatus includes memory banks, each having sub banks. The semiconductor memory apparatus is configured to allocate same test input/output line to a certain sub bank of one memory bank and a certain sub bank of another memory bank during a multi-bit test.

Abstract: A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.

Abstract: A data buffer control circuit and a semiconductor memory apparatus including the same are presented. The data buffer control circuit may include an internal command signal generator and a buffer enable signal generator. The internal command signal generator is configured to generate an internal command signal that is activated if delayed command signals are conditioned in a predetermined state of level combination. The buffer enable signal generator is configured to generate a buffer enable signal, which enables a data buffer receiving data in a writing mode, from the internal command signal in sync with a falling edge of an internal clock signal.

Abstract: A semiconductor integrated circuit according to one embodiment can include an up bank block that includes a first group of banks, a down bank block that includes a second group of banks, and a bank selection control block that provides up and down bank even-numbered global line control signals, up and down bank odd-numbered global line control signals, and up and down bank SDRAM write global line control signals in response to first and second group read control signals and a bank information signal in the up bank block and the down bank block. In this case, the bank selection control block may respond to a DDR signal and an SDR signal that are provided from an MRS (Mode Register Set).

Abstract: A data output circuit is provided which is capable of reducing a size and current consumption by commonly using a data output control unit for a plurality of data output units. The data output circuit includes a data output control unit for receiving an external clock signal and generate clock pulses having a pulse width, a first data output unit for outputting first data in synchronization with the clock pulse, and a second data output unit for outputting second data in synchronization with the clock pulses.