Abstract: A column address control circuit comprises a control unit for outputting a control signal in response to a DDR mode signal and a first signal, and an address counting unit configured to receive a start column address and output a start column address in response to the control signal. The first signal is a burst read single write mode signal. The control signal is activated when the first signal is activated in a DDR mode. The control unit includes a first logic unit for performing an AND operation of the DDR mode signal and the first signal, and a second logic unit for performing an OR operation of an output signal of the first logic unit and a SDR mode signal.

Abstract: A pipe latch circuit comprises a reset signal generating unit which receives a read-write flag signal and a read period signal and generates a reset signal, wherein the reset signal is enabled upon entry into a write operation or after all data are outputted to an outside upon read operation, an input/output control signal generating unit which generates a plurality of input control signals and output control signals in response to a read strobe signal and a clock signal, and is reset in response to the reset signal, and a pipe latch unit which latches inputted data in response to the input control signals and outputs the latched data in response to the output control signals.

Abstract: There is provided a command generation circuit. The command generation circuit includes a first driving unit driving an output node in response to an internal MRS command and a RAS idle signal; a second driving unit driving the output node in response to an off-signal; and a latch unit latching a signal at the output node in response to a power-up signal and generating an SRR command.

Abstract: A flash memory device includes a data input/output pad and a core region in which a plurality of unit cells are arranged. A data input buffer is configured to receive command and address data through the data input/output pad and transfer the received command and address to the core region. A data output buffer is configured to output the data through the data input/output pad, and a data input controller is configured to detect an outputting of the data and disable the data input buffer.

Abstract: A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.

Abstract: A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.

Abstract: A data output circuit is provided which is capable of reducing a size and current consumption by commonly using a data output control unit for a plurality of data output units. The data output circuit includes a data output control unit for receiving an external clock signal and generate clock pulses having a pulse width, a first data output unit for outputting first data in synchronization with the clock pulse, and a second data output unit for outputting second data in synchronization with the clock pulses.

Abstract: A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.

Abstract: A semiconductor memory apparatus includes a plurality of unit cell blocks formed in row and column directions, at least a pair of first input and output lines formed at predetermined intervals in the row direction, at least a pair of second input and output lines formed at predetermined intervals in the column direction, I/O switches connected to a first node group and a second node group and control data input and output of the first input and output lines and the second input and output lines, the first node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the odd-numbered intervals of the intervals between columns of unit cell blocks, and the second node group corresponding to half of the nodes in the row direction where the first input and output lines intersect the second input and output lines formed at the even-numbered intervals of the intervals between columns of unit cell blocks and a reset sele

Abstract: A semiconductor integrated circuit according to one embodiment can include an up bank block that includes a first group of banks, a down bank block that includes a second group of banks, and a bank selection control block that provides up and down bank even-numbered global line control signals, up and down bank odd-numbered global line control signals, and up and down bank SDRAM write global line control signals in response to first and second group read control signals and a bank information signal in the up bank block and the down bank block. In this case, the bank selection control block may respond to a DDR signal and an SDR signal that are provided from an MRS (Mode Register Set).

Abstract: A semiconductor package for forming a Double Die Package (DDP) with a plurality of single chips includes: a buffer configured to buffer an external address to generate a row address which is defined only in a DDP mode; a column address control unit configured to replace the row address with a column address, which is defined only in the DDP mode, in a single chip mode; and a read operation control unit configured to output a bank read signal latched in an active bank in a read mode of the DDP, and to selectively activate a first address control signal and a second address control signal for activating a bank selected from the single chip or the DDP in response to the bank read signal.

Abstract: A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.

Abstract: Disclosed is a semiconductor integrated circuit that allows a fail path to be detected. A semiconductor integrated circuit as described herein can be configured to include a data register that can receive input data to generate and store a write expectation value and a read expectation value, during a period in which a test mode is activated, a first comparing unit that compares write data written in a memory cell with the write expectation value, and a second comparing unit that compares read data read from the memory cell with the read expectation value.

Abstract: A column address control circuit comprises a control unit for outputting a control signal in response to a DDR mode signal and a first signal, and an address counting unit configured to receive a start column address and output a start column address in response to the control signal. The first signal is a burst read single write mode signal. The control signal is activated when the first signal is activated in a DDR mode. The control unit includes a first logic unit for performing an AND operation of the DDR mode signal and the first signal, and a second logic unit for performing an OR operation of an output signal of the first logic unit and a SDR mode signal.

Abstract: A semiconductor package for forming a Double Die Package (DDP) with a plurality of single chips includes: a buffer configured to buffer an external address to generate a row address which is defined only in a DDP mode; a column address control unit configured to replace the row address with a column address, which is defined only in the DDP mode, in a single chip mode; and a read operation control unit configured to output a bank read signal latched in an active bank in a read mode of the DDP, and to selectively activate a first address control signal and a second address control signal for activating a bank selected from the single chip or the DDP in response to the bank read signal.

Abstract: A flash memory device includes a data input/output pad and a core region in which a plurality of unit cells are arranged. A data input buffer is configured to receive command and address data through the data input/output pad and transfer the received command and address to the core region. A data output buffer is configured to output the data through the data input/output pad, and a data input controller is configured to detect an outputting of the data and disable the data input buffer.

Abstract: The present invention relates to a semiconductor memory, and more specifically, to a data output circuit capable of differentiating global data lines in accordance to an operation mode to output them to a data input/output pin. The present invention includes: a multiplexer selecting any one of a plurality of global input/output lines which can receive variable data bandwidth directed by control signals and which can output data carried on the selected global input/output line; a controller generating the control signals in accordance to operation mode signals corresponding to a data bandwidth and address signals provided for selecting data and providing them to the multiplexer; and a multiplexer driver amplifying the output of the multiplexer to transfer it to a data input/output pin. Thereby, the present invention can realize an improved data read speed by reducing the loading of the global input/output line.

Abstract: The present invention relates to a structure and method for transferring a column address. In transferring an external column address to the inside of a memory cell, a latch control unit controls the operation of a latch unit for latching the external column address signal. It is thus possible to prohibit consumption of current by controlling the operation of the latch unit when a read or write command signal is inputted.

Abstract: There is provided a semiconductor memory device capable of reducing power consumption by preventing unnecessary operations of an AL flip-flop delay unit and a CL flip-flop delay unit. The semiconductor memory device includes an internal column address generation means for receiving an external column address and generating an internal column address; a delay means for delaying the internal column address for a predetermined time corresponding to a preset latency; and a driving control means for driving the delay means for the predetermined time corresponding to the preset latency.

Abstract: The present invention relates to a structure and method for transferring a column address. In transferring an external column address to the inside of a memory cell, a latch control unit controls the operation of a latch unit for latching the external column address signal. It is thus possible to prohibit consumption of current by controlling the operation of the latch unit when a read or write command signal is inputted.