Abstract: The present invention relates to a method and system for providing language learning services. The method of providing language learning services, according to the present invention, the method may include: activating, in response to receiving an input for acquiring a learning target image through a user terminal, a camera of the user terminal; specifying at least a portion of an image taken by the camera as the learning target image; receiving language learning information for the learning target image from a server; providing the language learning information to the user terminal; and storing, based on a request for storing of the language learning information, the language learning information in association with the learning target image, such that the learning target image is used in conjunction with learning of the language learning information.

Abstract: The present invention relates to a method for preparing a 3D biological bilayer membrane structure in a physiological buffer solution and a 3D biological bilayer membrane structure using the same, and more particularly, to a method for preparing a 3D biological bilayer membrane structure that is tightly sealed even under physiological ionic conditions by applying pressure during electroformation to improve a membrane fusion function, and a 3D biological bilayer membrane structure using the same.

Abstract: A semiconductor memory device includes a substrate including an element separation film and an active region defined by the element separation film, a bit line structure on the substrate, a trench in the element separation film and the active region, the trench on at least one side of the bit line structure and including a first portion in the element separation film and a second portion in the active region, a bottom face of the first portion placed above a bottom face of the second portion, a single crystal storage contact filling the trench, and an information storage element electrically connected to the single crystal storage contact.

Abstract: A substrate processing method, involving etching a silicon nitride layer selectively in a substrate where a silicon oxide layer and the silicon nitride layer are stacked, includes: wet-etching the silicon nitride layer with a phosphoric acid-based etching solution; and dry-etching a regrowth oxide, which is formed on a surface of the silicon oxide layer in the wet etching step, with an etching gas.

Abstract: A display apparatus includes: a display panel including a display area, and a pad area adjacent to the display area; and a circuit board attached to the pad area. The pad area includes at least one signal pad terminal electrically connected to a first signal line extending through the display area, and at least one dummy pad terminal spaced from the first signal line. The circuit board includes a signal lead terminal connected to the signal pad terminal, and a dummy lead terminal connected to the dummy pad terminal.

Abstract: A semiconductor memory device includes a substrate including an element separation film and an active region defined by the element separation film, a bit line structure on the substrate, a trench in the element separation film and the active region, the trench on at least one side of the bit line structure and including a first portion in the element separation film and a second portion in the active region, a bottom face of the first portion placed above a bottom face of the second portion, a single crystal storage contact filling the trench, and an information storage element electrically connected to the single crystal storage contact.

Abstract: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.

Abstract: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.

Abstract: A semiconductor memory device includes a substrate including an element separation film and an active region defined by the element separation film, a bit line structure on the substrate, a trench in the element separation film and the active region, the trench on at least one side of the bit line structure and including a first portion in the element separation film and a second portion in the active region, a bottom face of the first portion placed above a bottom face of the second portion, a single crystal storage contact filling the trench, and an information storage element electrically connected to the single crystal storage contact.

Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Abstract: A semiconductor device includes a trench defining an active region in a substrate, a first insulating layer on a bottom surface and side surfaces of the active region inside the trench, a shielding layer on a surface of the first insulating layer, the shielding layer including a plurality of spaced apart particles, a second insulating layer on the shielding layer and having first charge trapped therein, the plurality of spaced apart particles being configured to concentrate second charge having an opposite polarity to the charge trapped in the second insulating layer, and a gap-fill insulating layer on the second insulating layer in the trench.

Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Abstract: A method of manufacturing a capacitor for a semiconductor device includes forming a lower electrode, forming a dielectric layer on the lower electrode, forming a first upper electrode on the dielectric layer, adsorbing an organic silicon source onto a surface of the first upper electrode, and forming a second upper electrode on the first upper electrode onto which the organic silicon source is adsorbed. Related devices and fabrication methods are also discussed.

Abstract: A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Abstract: A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

Abstract: A method of manufacturing a capacitor for a semiconductor device includes forming a lower electrode, forming a dielectric layer on the lower electrode, forming a first upper electrode on the dielectric layer, adsorbing an organic silicon source onto a surface of the first upper electrode, and forming a second upper electrode on the first upper electrode onto which the organic silicon source is adsorbed. Related devices and fabrication methods are also discussed.

Abstract: A precursor composition for forming a silicon dioxide film on a substrate, the precursor composition including at least one precursor compound represented by the following chemical formulas (1), (2), and (3): HxSiAy(NR1R2)4-x-y??(1) HxSi(NAR3)4-x??(2) HxSi(R4)z(R5)4-x-z??(3) wherein, independently in the chemical formulas (1), (2), and (3), H is hydrogen, x is 0 to 3, Si is silicon, A is a halogen, y is 1 to 4, N is nitrogen, and R1, R2, R3, and R5 are each independently selected from the group of H, aryl, perhaloaryl, C1-8 alkyl, and C1-8 perhaloalkyl, and R4 is aryl in which at least one hydrogen is replaced with a halogen or C1-8 alkyl in which at least one hydrogen is replaced with a halogen.