Patents by Inventor Bong-Hyun Kim

Bong-Hyun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7297620
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Publication number: 20070085207
    Abstract: A pad structure, a method of forming a pad structure, a semiconductor device having a pad structure and a method of manufacturing a semiconductor device are disclosed. The pad structure may include a first pad, a second pad, a third pad and/or a spacer. The first pad may contact a contact region on a substrate. The first pad may include doped polysilicon. The second pad may contact the first pad. The second pad may include a metal silicide or a metal silicongermanium. The third pad may contact the second pad. The third pad may include a conductive material (e.g., doped polysilicon, a metal or a metal nitride). The spacer may be formed on sidewalls of the second and the third pads.
    Type: Application
    Filed: August 2, 2006
    Publication date: April 19, 2007
    Inventors: Woo-Sung Lee, Young-Wook Park, Nam-Kyu Kim, Bong-Hyun Kim, Man-Sug Kang
  • Publication number: 20070070294
    Abstract: The present invention is related to an image acquisition/output apparatus and a picture system for ophthalmic operation using the same. The picture system for ophthalmic operation according to the present invention includes a near-infrared microscope for irradiating an affect part through an objective lens with near-infrared ray emitted from a light source, and transmitting near-infrared images formed by the objective lens to a first and a second ocular lenses, an image acquisition apparatus for converting near-infrared images transmitted to the first and the second ocular lenses into a first and a second electrical image signals for output, and a display apparatus for receiving the first and the second image signals and outputting them in three-dimensional images.
    Type: Application
    Filed: February 28, 2005
    Publication date: March 29, 2007
    Inventor: Bong-Hyun Kim
  • Publication number: 20070010068
    Abstract: Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 11, 2007
    Inventors: Yong-Sun Lee, Jai-Dong Lee, Bong-Hyun Kim, Man-Sug Kang, Jung-Hwan Kim, Hyun-Jin Shin, Won-Seok Yoo, Seung-Mok Shin
  • Patent number: 7008844
    Abstract: A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: March 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Hyun Kim, Hun-Hyeoung Lim, Hyeon-Deok Lee, Yong-Woo Hyung
  • Patent number: 7008876
    Abstract: A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: March 7, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Sung Lee, Bong-Hyun Kim, Myang-Sik Han, Eun-Kuk Chung
  • Publication number: 20050250343
    Abstract: An insulation layer containing bonds of Si—N may be formed on a substrate. An electrode may be formed on the insulation layer. The substrate and the insulation layer exposed by the electrode may be treated with free radicals, which may improve the insulation capacity of the insulation layer and/or partially oxidize a surface of the substrate. The bonds of Si—N may be transformed into bonds of Si—O such that damage to the substrate and the insulation layer may be cured.
    Type: Application
    Filed: May 10, 2005
    Publication date: November 10, 2005
    Inventors: Kong-Soo Lee, Sang-Jin Park, Bong-Hyun Kim, Ki-Hyun Hwang
  • Patent number: 6913979
    Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: July 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hyeon-Deok Lee, Tae-Soo Park, Heon-Heoung Leam, Bong-Hyun Kim, Yong-Woo Hyung
  • Patent number: 6905927
    Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: June 14, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Young Ahn, Bong-Hyun Kim, Jae-Duk Lee, Man-Sug Kang
  • Publication number: 20040266217
    Abstract: A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.
    Type: Application
    Filed: June 23, 2004
    Publication date: December 30, 2004
    Inventors: Kyoung-seok Kim, Hong-bae Park, Bong-hyun Kim, Sung-tae Kim, Jong-wan Kwon, Jung-hyun Lee, Ki-chul Kim, Jae-soon Lim, Gab-jin Nam, Young-sun Kim
  • Publication number: 20040224531
    Abstract: In methods of forming an oxide layer and an oxynitride layer, a substrate is loaded into a reaction chamber having a first pressure and a first temperature. The oxide layer is formed on the substrate using a reaction gas while increasing a temperature of the reaction chamber from the first temperature to a second temperature under a second pressure. Additionally, the oxide layer is nitrified in the reaction chamber to form the oxynitride layer on the substrate. When the oxide layer and/or the oxynitride layer are formed on the substrate, minute patterns of a semiconductor device, for example a DRAM device, an SRAM device or an LOGIC device may be easily formed on the oxide layer or the oxynitride layer.
    Type: Application
    Filed: May 6, 2004
    Publication date: November 11, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hun-Hyeoung Leam, Seok-Woo Nam, Bong-Hyun Kim, Woong Lee, Sang-Hoon Lee
  • Publication number: 20040166616
    Abstract: A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 26, 2004
    Inventors: Woo-Sung Lee, Bong-Hyun Kim, Myang-Sik Han, Eun-Kuk Chung
  • Publication number: 20040087123
    Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o
    Type: Application
    Filed: October 7, 2003
    Publication date: May 6, 2004
    Inventors: Jae-Young Ahn, Bong-Hyun Kim, Jae-Duk Lee, Man-Sug Kang
  • Publication number: 20040058556
    Abstract: Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.
    Type: Application
    Filed: April 30, 2003
    Publication date: March 25, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Sub You, Hyeon-Deok Lee, Tae-Soo Park, Heon-Heoung Leam, Bong-Hyun Kim, Yong-Woo Hyung
  • Publication number: 20040033653
    Abstract: A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 19, 2004
    Inventors: Bong-Hyun Kim, Hun-Hyeoung Lim, Hyeon-Deok Lee, Yong-Woo Hyung
  • Patent number: 6660587
    Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: December 9, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Young Ahn, Bong-Hyun Kim, Jae-Duk Lee, Man-Sug Kang
  • Publication number: 20030022488
    Abstract: A semiconductor device and method of production are disclosed, the method including forming a preliminary gate electrode on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and performing a re-oxidation process for curing damage of the semiconductor substrate and/or a sidewall of the conductive layer pattern, when the preliminary gate electrode is formed by forming an oxide layer on an outer surface of the preliminary gate electrode and on the semiconductor substrate, by supplying an oxygen gas and a chlorine-including gas while restraining a thickness of the gate oxide layer pattern from being increased; and the semiconductor device comprising a preliminary gate electrode formed on a semiconductor substrate, the preliminary gate electrode including a gate oxide layer pattern and a conductive layer pattern stacked on the gate oxide layer pattern, and a re-oxidized semiconductor substrate and/o
    Type: Application
    Filed: July 26, 2002
    Publication date: January 30, 2003
    Applicant: Sumsung Electronics Co., Ltd.
    Inventors: Jae-Young Ahn, Bong-Hyun Kim, Jae-Duk Lee, Man-Sug Kang