Patents by Inventor Bong Soo Kim

Bong Soo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121383
    Abstract: A separator for a fuel cell having a flow channel including a transverse channel and a longitudinal channel formed therein, the transverse channel having a pair of opposed side walls, and a first pattern and a second pattern alternately spaced and arranged in the transverse channel is provided. Each of the first pattern and the second pattern is a column-shaped three-dimensional structure having a polygonal transverse section. The first pattern and the second pattern are arranged in the transverse channel so as to have a shape of the transverse sections being rotated 180° relative to each other. First spacing distances from each of the first pattern and the second pattern to a first side wall of the pair of opposed side walls of the transverse channel are different.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: September 14, 2021
    Assignee: LG CHEM, LTD.
    Inventors: Bong Soo Kim, Jee Hoon Jeong, Kyung Mun Kang, Jae Choon Yang
  • Patent number: 11106630
    Abstract: An operating method of a host includes receiving a request for secure deletion of a first file stored in a storage system, providing an invalidation command to the storage system for invalidating data of the first file, providing an erase command to the storage system for erasing invalidated data included in the storage system, and performing a deletion operation, which is executable on an operating system of the host, on the first file which is deleted by the erase command.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: August 31, 2021
    Inventors: Jin-hwan Park, Chan-sol Kim, Myung-jin Jung, Ji-soo Kim, Kyung-ho Kim, Pil-sung Kang, Bong-jun Choi, Chae-won Yu, So-jeong Lee
  • Publication number: 20210249417
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Hui-Jung Kim, Min Hee Cho, Bong-Soo Kim, Junsoo Kim, Satoru Yamada, Wonsok Lee, Yoosang Hwang
  • Publication number: 20210249418
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 12, 2021
    Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Taejin Park, Yoosang Hwang
  • Publication number: 20210210432
    Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.
    Type: Application
    Filed: March 18, 2021
    Publication date: July 8, 2021
    Inventors: Eunjung Kim, Hui-Jung Kim, Keunnam Kim, Daeik Kim, Bong-soo Kim, Yoosang Hwang
  • Publication number: 20210202486
    Abstract: A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Sung Hwan KIM, Ji Young KIM, Bong Soo KIM
  • Publication number: 20210151757
    Abstract: A sulfur-carbon composite and a lithium secondary battery including the same are discussed. More specifically, a network-shaped coating layer including a conductive polymer is formed on a surface of the sulfur-carbon composite, and thus the conductivity of the sulfur-carbon composite is enhanced and also, lithium ions move freely, and accordingly, when applied to lithium secondary batteries, the sulfur-carbon composite can enhance the performance of batteries.
    Type: Application
    Filed: September 10, 2019
    Publication date: May 20, 2021
    Applicant: LG Chem, Ltd.
    Inventors: Bong Soo KIM, Kwonnam SOHN
  • Publication number: 20210143154
    Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.
    Type: Application
    Filed: December 18, 2020
    Publication date: May 13, 2021
    Inventors: KISEOK LEE, BONG-SOO KIM, JIYOUNG KIM, HUI-JUNG KIM, SEOKHAN PARK, HUNKOOK LEE, YOOSANG HWANG
  • Patent number: 10998322
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 4, 2021
    Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Taejin Park, Yoosang Hwang
  • Publication number: 20210125998
    Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.
    Type: Application
    Filed: August 11, 2020
    Publication date: April 29, 2021
    Inventors: SEOK-HYUN KIM, Joon Young KANG, YOUNGJUN KIM, JINHYUNG PARK, HO-JU SONG, SANG-JUN LEE, HYERAN LEE, BONG-SOO KIM, SUNGWOO KIM
  • Patent number: 10991699
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 27, 2021
    Inventors: Hui-Jung Kim, Min Hee Cho, Bong-Soo Kim, Junsoo Kim, Satoru Yamada, Wonsok Lee, Yoosang Hwang
  • Patent number: 10978397
    Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: April 13, 2021
    Inventors: Eunjung Kim, Hui-Jung Kim, Keunnam Kim, Daeik Kim, Bong-soo Kim, Yoosang Hwang
  • Patent number: 10971496
    Abstract: A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Hwan Kim, Ji Young Kim, Bong Soo Kim
  • Patent number: 10943812
    Abstract: A semiconductor device includes a first trench on the device region, a first device isolation layer in the first trench and defining an active pattern of the device region, a second trench on the interface region, and a second device isolation layer in the second trench. The second isolation layer includes a buried dielectric pattern, a dielectric liner pattern on the buried dielectric pattern, and a first gap-fill dielectric pattern on the dielectric liner pattern. The buried dielectric pattern includes a floor segment on a floor of the second trench, and a sidewall segment on a sidewall of the second trench. The sidewall segment has a thickness different from a thickness of the floor segment.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Semyeong Jang, Bong-Soo Kim, Heejae Chae
  • Publication number: 20210057416
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.
    Type: Application
    Filed: November 5, 2020
    Publication date: February 25, 2021
    Inventors: Jiyoung KIM, Kiseok LEE, Bong-Soo KIM, Junsoo KIM, Dongsoo WOO, Kyupil LEE, HyeongSun HONG, Yoosang HWANG
  • Publication number: 20210057735
    Abstract: A sulfur-carbon composite, a preparation method thereof, a positive electrode, and a lithium secondary battery including the same are disclosed. The sulfur-carbon composite has a fluorine-based surfactant and sulfur sequentially forming a double coating layer on the surface of a porous carbon material and/or on an inner surface of pores of the porous carbon material, and thus when the sulfur-carbon composite is applied to a positive electrode of a lithium secondary battery, for example, a lithium-sulfur secondary battery, the fluorine-based surfactant can be slowly dissolved to prevent deterioration of lithium contained in the negative electrode, and the surface energy of the electrolyte solution can be lowered to improve the wettability of the positive electrode, thereby improving the lifetime of the battery.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 25, 2021
    Applicant: LG CHEM, LTD.
    Inventors: Bong Soo KIM, Soohyun KIM, Sun Mi JIN
  • Patent number: 10910378
    Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: February 2, 2021
    Inventors: Kiseok Lee, Bong-Soo Kim, Jiyoung Kim, Hui-Jung Kim, Seokhan Park, Hunkook Lee, Yoosang Hwang
  • Patent number: 10896966
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a buried gate structure located on a first recess in the first region of the substrate, and a recess gate structure located on a second recess in the second region of the substrate, wherein the buried gate structure is buried in the substrate, an upper portion of the recess gate structure is not buried in the substrate, and a first work function adjustment layer in the buried gate structure may include a material identical to a material included in a second work function layer of the recess gate structure.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-jin Lee, Bong-soo Kim, Ji-young Kim, Ho-rim Yoo
  • Patent number: D929435
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: August 31, 2021
    Assignee: Hyundai Mobis Co., Ltd.
    Inventors: Bong Geun Jeon, Hyung Soo Kim, Bo Young Park, Seo Hyun Kim, Min Hee Kim
  • Patent number: D930023
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: September 7, 2021
    Assignee: HYUNDAI MOBIS CO., LTD.
    Inventors: Seo Hyun Kim, Hyung Soo Kim, Bo Young Park, Bong Geun Jeon, Min Hee Kim