Patents by Inventor Bong Soo Kim
Bong Soo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190355813Abstract: Provided are semiconductor devices including device isolation layers. The semiconductor device includes a substrate having a cell region and a core/peripheral region, a first active region in the cell region of the substrate, a first device isolation layer that defines the first active region, a second active region in the core/peripheral region of the substrate; and a second device isolation layer that defines the second active region. A height from a lower surface of the substrate to an upper end of the first device isolation layer in a first direction that is perpendicular to the lower surface of the substrate is less than or equal to a height from the lower surface of the substrate to an upper end of the first active region in the first direction.Type: ApplicationFiled: December 12, 2018Publication date: November 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Se-myeong JANG, Jun-hyeok AHN, Bong-soo KIM, Hyo-bin PARK, Myoung-seob SHIM
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Patent number: 10483346Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.Type: GrantFiled: August 29, 2018Date of Patent: November 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-hyung Nam, Bong-Soo Kim, Yoosang Hwang
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Patent number: 10468350Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.Type: GrantFiled: May 11, 2017Date of Patent: November 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Eunjung Kim, Hui-Jung Kim, Keunnam Kim, Daeik Kim, Bong-soo Kim, Yoosang Hwang
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Patent number: 10468414Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate and a stack including a plurality of layers on the substrate. Each of the plurality of layers includes semiconductor patterns and a first conductive line that is connected to at least one of the semiconductor patterns. A second conductive line and a third conductive line penetrate the stack. The semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern that are adjacent and spaced apart from each other in a first layer among the plurality of layers. The third conductive line is between, and connected in common to, the first and second semiconductor patterns.Type: GrantFiled: August 29, 2018Date of Patent: November 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hui-Jung Kim, Kiseok Lee, Junsoo Kim, Sunghee Han, Bong-Soo Kim, Yoosang Hwang
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Patent number: 10461153Abstract: A semiconductor memory device includes a substrate including active regions, word lines in the substrate and each extending in a first direction parallel to an upper surface of the substrate, bit line structures connected to the active regions, respectively, and each extending in a second direction crossing the first direction, and spacer structures on sidewalls of respective ones of the bit line structures. Each of the spacer structures includes a first spacer, a second spacer, and a third spacer. The second spacer is disposed between the first spacer and the third spacer and includes a void defined by an inner surface of the second spacer. A height of the second spacer is greater than a height of the void.Type: GrantFiled: February 7, 2018Date of Patent: October 29, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Kiseok Lee, Myeong-Dong Lee, Hui-Jung Kim, Dongoh Kim, Bong-Soo Kim, Seokhan Park, Woosong Ahn, Sunghee Han, Yoosang Hwang
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Publication number: 20190325930Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.Type: ApplicationFiled: July 2, 2019Publication date: October 24, 2019Inventors: SUNGWOO KIM, BONG-SOO KIM, YOUNGBAE KIM, KIJAE HUR, GWANHYEOB KOH, HYEONGSUN HONG, YOOSANG HWANG
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Publication number: 20190325960Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: SUNGWOO KIM, BONG-SOO KIM, YOUNGBAE KIM, KIJAE HUR, GWANHYEOB KOH, HYEONGSUN HONG, YOOSANG HWANG
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Patent number: 10446560Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.Type: GrantFiled: May 22, 2018Date of Patent: October 15, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungwoo Kim, Bong-Soo Kim, Youngbae Kim, Kijae Hur, Gwanhyeob Koh, Hyeongsun Hong, Yoosang Hwang
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Publication number: 20190287977Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.Type: ApplicationFiled: May 22, 2019Publication date: September 19, 2019Inventors: Kiseok LEE, Chan-Sic YOON, Augustin HONG, Keunnam KIM, Dongoh KIM, Bong-Soo KIM, Jemin PARK, Hoin LEE, Sungho JANG, Kiwook JUNG, Yoosang HWANG
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Patent number: 10410722Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.Type: GrantFiled: May 23, 2018Date of Patent: September 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungwoo Kim, Bong-Soo Kim, Youngbae Kim, Kijae Hur, Gwanhyeob Koh, Hyeongsun Hong, Yoosang Hwang
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Patent number: 10395706Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.Type: GrantFiled: May 21, 2018Date of Patent: August 27, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungwoo Kim, Bong-Soo Kim, Youngbae Kim, Kijae Hur, Gwanhyeob Koh, Hyeongsun Hong, Yoosang Hwang
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Publication number: 20190252386Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.Type: ApplicationFiled: February 6, 2019Publication date: August 15, 2019Inventors: KISEOK LEE, BONG-SOO KIM, JIYOUNG KIM, HUI-JUNG KIM, SEOKHAN PARK, HUNKOOK LEE, YOOSANG HWANG
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Publication number: 20190229348Abstract: A separator for a fuel cell having a flow channel including a transverse channel and a longitudinal channel formed therein, the transverse channel having a pair of opposed side walls, and a first pattern and a second pattern alternately spaced and arranged in the transverse channel is provided. Each of the first pattern and the second pattern is a column-shaped three-dimensional structure having a polygonal transverse section. The first pattern and the second pattern are arranged in the transverse channel so as to have a shape of the transverse sections being rotated 180° relative to each other. First spacing distances from each of the first pattern and the second pattern to a first side wall of the pair of opposed side walls of the transverse channel are different.Type: ApplicationFiled: October 12, 2017Publication date: July 25, 2019Applicant: LG CHEM, LTD.Inventors: Bong Soo KIM, Jee Hoon JEONG, Kyung Mun KANG, Jae Choon YANG
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Publication number: 20190214293Abstract: A method of fabricating a semiconductor device includes preparing a substrate including a cell region and a peripheral region having different active region densities, forming cell trenches for limiting cell active regions in the cell region so that the cell active regions are formed to be spaced apart by a first width in a first direction and by a second width in a second direction, forming peripheral trenches for limiting a peripheral active region in the peripheral region, and forming, in the cell trenches, a first insulating layer continuously extending in the first and second directions and contacting sidewalls of the cell active regions, and having a thickness equal to or greater than half of the first width and less than half of the second width.Type: ApplicationFiled: July 6, 2018Publication date: July 11, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Kyu Jin Kim, Min Su Choi, Sung Hee Han, Bong Soo Kim, Yoo Sang Hwang
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Publication number: 20190206983Abstract: A semiconductor device including a plurality of pillars on a semiconductor substrate; and a support pattern in contact with some lateral surfaces of the pillars and connecting the pillars with one another, wherein the support pattern includes openings that expose other lateral surfaces of the pillars, each of the pillars includes a first pillar upper portion in contact with the support pattern and a second pillar upper portion spaced apart from the support pattern, and the second pillar upper portion has a concave slope.Type: ApplicationFiled: August 29, 2018Publication date: July 4, 2019Inventors: Ki-hyung NAM, Bong-Soo KIM, Yoosang HWANG
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Publication number: 20190206869Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate and a stack including a plurality of layers on the substrate. Each of the plurality of layers includes semiconductor patterns and a first conductive line that is connected to at least one of the semiconductor patterns. A second conductive line and a third conductive line penetrate the stack. The semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern that are adjacent and spaced apart from each other in a first layer among the plurality of layers. The third conductive line is between, and connected in common to, the first and second semiconductor patterns.Type: ApplicationFiled: August 29, 2018Publication date: July 4, 2019Inventors: Hui-Jung Kim, Kiseok Lee, Junsoo Kim, Sunghee Han, Bong-Soo Kim, Yoosang Hwang
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Publication number: 20190206875Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.Type: ApplicationFiled: March 7, 2019Publication date: July 4, 2019Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Taejin Park, Yoosang Hwang
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Patent number: 10332890Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.Type: GrantFiled: July 18, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kiseok Lee, Chan-Sic Yoon, Augustin Hong, Keunnam Kim, Dongoh Kim, Bong-Soo Kim, Jemin Park, Hoin Lee, Sungho Jang, Kiwook Jung, Yoosang Hwang
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Patent number: 10332831Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.Type: GrantFiled: June 30, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Augustin Jinwoo Hong, Dae-Ik Kim, Chan-Sic Yoon, Ki-Seok Lee, Dong-Min Han, Sung-Ho Jang, Yoo-Sang Hwang, Bong-Soo Kim, Je-Min Park
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Publication number: 20190189550Abstract: A fan-out semiconductor package includes: a core member having a through-hole; a semiconductor chip disposed in the through-hole of the core member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant covering at least portions of the core member and the semiconductor chip and filling at least portions of the through-hole; and a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The core member has a recess portion penetrating through at least portions of the core member, and at least a portion of the recess portion is filled with the encapsulant.Type: ApplicationFiled: July 17, 2018Publication date: June 20, 2019Inventor: Bong Soo KIM