Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Abstract: A memory device includes an array of vertical NAND strings of nonvolatile memory cells, on an underlying substrate. An erase control circuit is provided, which is configured to drive a plurality of bit lines electrically coupled to the array of vertical NAND strings of nonvolatile memory cells with respective erase voltages having unequal magnitudes during an operation to erase the nonvolatile memory cells in the array of vertical NAND strings. This erase control circuit may also be configured to drive a first of the plurality of bit lines with a first erase voltage for a first duration and drive a second of the plurality of bit lines with a second erase voltage for a second duration unequal to the first duration during the operation to erase the nonvolatile memory cells in the array of vertical NAND strings.

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a first substrate, a horizontal semiconductor layer disposed on a second substrate, a plurality of stack structures on the horizontal semiconductor layer in a first direction, wherein the plurality of stack structures include a memory cell region and a capacitor region, a plurality of electrode isolation regions extending in the first direction and a second direction and configured to separate the plurality of stack structures to be connected to the horizontal semiconductor layer and a plurality of through-via structures having a first side connected to a through channel contact through at least one metal pad, wherein a capacitor is formed between each of electrode pads and at least one of electrode isolation regions in the plurality of stack structures or at least one of the plurality of through-via structures.

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure on a substrate and including a peripheral circuits, horizontal semiconductor layers on the peripheral logic structure, a stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, electrode isolation regions separating the stack structures and extending in the first direction and a second direction, the electrode isolation regions being connected to the horizontal semiconductor layers, and through-via structures in the peripheral logic structure. The through-via structures penetrate the stack structures in the first direction. Each of the through-via structures have one side connected to a corresponding one of the through channel contacts. Capacitors are formed by electrode pads respectively with at least one of the electrode isolation regions or with at least one of the through-via structures.

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

Abstract: A semiconductor device includes a first semiconductor chip, a second semiconductor chip, an input/output circuit, a sensing line, and a detecting circuit. The first semiconductor chip includes bitlines, wordlines, first bonding pads electrically connected to the bitlines, second bonding pads electrically connected to the wordlines, and memory cells electrically connected to the bitlines and the wordlines. The second semiconductor chip includes third bonding pads that are electrically connected to the first bonding pads and fourth bonding pads that are electrically connected to the second bonding pads. The input/output circuit writes data to the memory cells via the third bonding pads. The sensing line extends along edge portions of at least one of the first and second semiconductor chips. The detecting circuit is in the second semiconductor chip and can detect defects from at least one of the first and second semiconductor chips using the sensing line.

Abstract: A semiconductor device includes a first semiconductor chip including bitlines, wordlines, common source line, first bonding pads, second bonding pads, third bonding pads and memory cells, the memory cells being electrically connected to the bitlines, the wordlines, and the common source line, the first bonding pads being electrically connected to the bitlines, the second bonding pads being electrically connected to the wordlines, and the third bonding pads being electrically connected to the common source line; a second semiconductor chip including fourth bonding pads, fifth bonding pads, sixth bonding pads and an input/output circuit, the fourth bonding pads being electrically connected to the first bonding pads, the fifth bonding pads being electrically connected to the second bonding pads, the sixth bonding pads being electrically connected to the third bonding pads and the input/output circuit being configured to write data to the memory cells via the fourth bonding pads and the fifth bonding pads; a sens

Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell army, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the

Abstract: A nonvolatile memory includes a first sub-block defined by a first string select line and a first word line; a second sub-block defined by a second string select line different from the first string select line and a second word line different from the first word line; a first vacant block defined by the first string select line and the second word line; and a second vacant block defined by the second string select line and the first word line. First data is programmed in the first sub-block with, second data is programmed in the second sub-block, and no data is programmed in the first vacant block and the second vacant block.

Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Abstract: In a method of erasing data in a nonvolatile memory device including a memory block, it is determined whether a data erase characteristic for the memory block is degraded for each predetermined cycle. The memory block has a plurality of memory cells therein, the plurality of memory cells being stacked in a vertical direction relative to an underlying substrate. A data erase operation is performed by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.

Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.

Abstract: A method of operating a nonvolatile memory device is provided where the nonvolatile memory device includes a plurality of cell strings, and each cell string includes a plurality of multi-level cells. a voltage of a selected word line is sequentially changed to sequentially have a plurality of read voltages for determining threshold voltage states of the plurality of multi-level cells. A voltage of an adjacent word line adjacent to the selected word line is sequentially changed in synchronization with voltage changing time points of the selected word line. A load of the selected word line is reduced and an operation speed of the nonvolatile memory device is increased by synchronizing the voltage change of the selected word line and the voltage change of the adjacent word line in the same direction.

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.

Abstract: A nonvolatile memory device and a method of manufacturing the device, the device including a first semiconductor layer, the first semiconductor layer including an upper substrate, and a memory cell array, the memory cell array including a plurality of gate conductive layers stacked on the upper substrate and a plurality of pillars passing through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the upper substrate; and a second semiconductor layer under the first semiconductor layer, the second semiconductor layer including a lower substrate, at least one contact plug between the lower substrate and the upper substrate, and a common source line driver on the lower substrate and configured to output a common source voltage for the plurality of pillars through the at least one contact plug.

Abstract: A nonvolatile memory device including: a first semiconductor layer including word lines, bit lines, first and second upper substrates adjacent to each other and a memory cell array, wherein the memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate; and a second semiconductor layer under the first semiconductor layer, wherein the second semiconductor layer includes a lower substrate that includes row decoder and page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area.