Abstract: A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

Abstract: A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

Abstract: A resistive-type memory device is disclosed. The resistive-type memory device includes a memory cell array and a control logic circuit. The control logic circuit accesses the memory cell array in response to a command and an address provided from an outside. The memory cell array includes at least a first group of resistive-type memory cells and a second group of resistive-type memory cells. Each of the first group of resistive-type memory cells has a first feature size and each of the second group of resistive-type memory cells has a second feature size that is different from the first feature size.

Abstract: Magnetic random access memory (MRAM)-based frame buffering apparatus are provided that may reduce a size and power consumption thereof by using a pixel self-refresh (PSR) method. The MRAM-based frame buffering apparatus includes a frame buffer memory including magnetic random access memory (MRAM). The frame buffer memory stores at least one piece of frame data. The MRAM-based frame buffering apparatus further includes a magnetic field sensor configured to detect an external magnetic field; and a frame buffer controller configured to control the storing of the at least one piece of frame data according to the intensity of the detected external magnetic field.

Abstract: A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.

Abstract: A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.

Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Abstract: A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.

Abstract: A magnetic random-access memory (MRAM) device and a semiconductor package include a magnetic shielding layer that may suppress at least one of magnetic orientation errors and deterioration of magnetic tunnel junction (MTJ) structures due to external magnetic fields. A semiconductor device includes: a MRAM chip including a MRAM; and a magnetic shielding layer including an upper shielding layer and a via shielding layer. The upper shielding layer is on a top surface of the MRAM chip, and the via shielding layer extends from the upper shielding layer and passes through the MRAM chip.

Abstract: Magnetic random access memory (MRAM)-based frame buffering apparatus are provided that may reduce a size and power consumption thereof by using a pixel self-refresh (PSR) method. The MRAM-based frame buffering apparatus includes a frame buffer memory including magnetic random access memory (MRAM). The frame buffer memory stores at least one piece of frame data. The MRAM-based frame buffering apparatus further includes a magnetic field sensor configured to detect an external magnetic field; and a frame buffer controller configured to control the storing of the at least one piece of frame data according to the intensity of the detected external magnetic field.

Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Abstract: Provided is a method and apparatus for controlling a plurality of memory devices. According to various embodiments of the present disclosure, there is provided an electronic device. The electronic device includes a first memory and a second memory, and a processor that is functionally connected with the first memory and the second memory. The processor is configured to determine at least one state associated with the electronic device, and allocate at least a partial area of one of the first memory and the second memory to at least some data of at least one process to be executed in the electronic device based on the at least one state. Other embodiments are possible.

Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Abstract: A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical connections between source lines and a source voltage in response to the floating control signals in a read operation. Related devices and methods are also described.

Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.