Patents by Inventor Brad D. Rumsey

Brad D. Rumsey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7951646
    Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: May 31, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Brad D. Rumsey, Patrick W. Tandy, Willam J. Reeder, Stephen F. Moxham, Steven G. Thummel, Dana A. Stoddard, Joseph C. Young
  • Patent number: 7335571
    Abstract: A method for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial are also described.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: February 26, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 7307850
    Abstract: A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing. The second openings expose selective regions of a conductor layer. The multi-layer circuit board provides for less occurrences of delamination.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: December 11, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 7263768
    Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: September 4, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 7255273
    Abstract: The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is inspected and tested for visual and electrical defects. Information relating to the functionality and/or various defects of one or more die sites is then encoded in the form of a designator placed on the substrate. The information encoded on the designator may then be read or scanned by, for example, computer-driven video equipment and used in a die-attach process to discriminately place semiconductor dice only on known good die sites. Embodiments of the designator include information encoded in the form of a bar code, a series of identifying marks, a strip of magnetic tape or a computerized map of a mounting substrate. Correlated data regarding die site functionality can then be electronically transferred to a die-bonding apparatus.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: August 14, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 7146720
    Abstract: A method for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate using the combination pin one indicator and alignment fiducial are also described.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: December 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 7127365
    Abstract: The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is inspected and tested for visual and electrical defects. Information relating to the functionality and/or various defects of one or more die sites is then encoded in the form of a designator placed on the substrate. The information encoded on the designator may then be read or scanned by, for example, computer-driven video equipment and used in a die-attach process to discriminately place semiconductor dice only on known good die sites. Embodiments of the designator include information encoded in the form of a bar code, a series of identifying marks, a strip of magnetic tape or a computerized map of a mounting substrate. Correlated data regarding die site functionality can then be electronically transferred to a die-bonding apparatus.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: October 24, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 7115819
    Abstract: A solder mask defined bond pad or a non-solder mask defined bond pad may be configured to center the solder over the bond pad using either surface attractive forces or capillary action. In some embodiments, a stub trace may be provided, for example, in opposition to the real trace to provide a capillary counter-attractive force on the solder. In other embodiments, the surface attractive action of the edge of the solder mask may be utilized to center the solder. In still other embodiments, the natural attractive force of a trace on solder may be utilized to appropriately position solder where desired, for example, to line up with other solder deposits.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: October 3, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 7088590
    Abstract: A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing. The second openings expose selective regions of a conductor layer. The multi-layer circuit board provides for less occurrences of delamination.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: August 8, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 7019223
    Abstract: The present invention features a novel design for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: March 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 7013559
    Abstract: The present invention features a novel design for forming a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: March 21, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 6984894
    Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: January 10, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 6914326
    Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: July 5, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Patrick W. Tandy, Willam J. Reeder, Stephen F. Moxham, Steven G. Thummel, Dana A. Stoddard, Joseph C. Young
  • Patent number: 6889902
    Abstract: The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is inspected and tested for visual and electrical defects. Information relating to the functionality and/or various defects of one or more die sites is then encoded in the form of a designator placed on the substrate. The information encoded on the designator may then be read or scanned by, for example, computer-driven video equipment and used in a die-attach process to discriminately place semiconductor dice only on known good die sites. Embodiments of the designator include information encoded in the form of a bar code, a series of identifying marks, a strip of magnetic tape or a computerized map of a mounting substrate. Correlated data regarding die site functionality can then be electronically transferred to a die-bonding apparatus.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: May 10, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 6790708
    Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: September 14, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Publication number: 20040105291
    Abstract: A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing. The second openings expose selective regions of a conductor layer. The multi-layer circuit board provides for less occurrences of delamination.
    Type: Application
    Filed: November 25, 2003
    Publication date: June 3, 2004
    Applicant: Micron Technology, Inc.
    Inventor: Brad D. Rumsey
  • Patent number: 6734372
    Abstract: A method and device for providing a relief area on the surface of a molded I/C package. Specifically, a method of reducing delamination at the gate area of a molded I/C package by disposing an area of patterned metal traces on the substrate surface to form a relief area. The relief area will permit the I/C package to be broken away form the molding apparatus while reducing the possibility of delamination or Au/Cu burs at the gate area.
    Type: Grant
    Filed: April 23, 2002
    Date of Patent: May 11, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Stephen L. James, Richard W. Wensel, Brad D. Rumsey
  • Publication number: 20040030517
    Abstract: The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is inspected and tested for visual and electrical defects. Information relating to the functionality and/or various defects of one or more die sites is then encoded in the form of a designator placed on the substrate. The information encoded on the designator may then be read or scanned by, for example, computer-driven video equipment and used in a die-attach process to discriminately place semiconductor dice only on known good die sites. Embodiments of the designator include information encoded in the form of a bar code, a series of identifying marks, a strip of magnetic tape or a computerized map of a mounting substrate. Correlated data regarding die site functionality can then be electronically transferred to a die-bonding apparatus.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 12, 2004
    Inventor: Brad D. Rumsey
  • Publication number: 20040026515
    Abstract: The present invention relates to the marking and identification of defective die sites on a mounting substrate. A mounting substrate is provided which is inspected and tested for visual and electrical defects. Information relating to the functionality and/or various defects of one or more die sites is then encoded in the form of a designator placed on the substrate. The information encoded on the designator may then be read or scanned by, for example, computer-driven video equipment and used in a die-attach process to discriminately place semiconductor dice only on known good die sites. Embodiments of the designator include information encoded in the form of a bar code, a series of identifying marks, a strip of magnetic tape or a computerized map of a mounting substrate. Correlated data regarding die site functionality can then be electronically transferred to a die-bonding apparatus.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 12, 2004
    Inventor: Brad D. Rumsey
  • Patent number: 6690086
    Abstract: A method for inhibiting damage caused to semiconductor die packages during a molding process, and the semiconductor die packages formed therefrom, is described. One or more openings are provided in a die carrier which are filled with a material which is more resistant to compressive forces than the carrier.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: February 10, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Stephen L. James, Brad D. Rumsey