Abstract: A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing. The second openings expose selective regions of a conductor layer. The multi-layer circuit board provides for less occurrences of delamination.

Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided. Preferably, the pin one indicator/alignment fiducial is placed adjacent a comer area of a ball grid array, and comprises an “L”-shaped narrow opening in a solder mask layer in which two lines, mutually perpendicular to one another, form components of an X-Y axis. The pin one indicator/alignment fiducial of the present invention is configured to provide only a minimal opening in the solder resist, making smaller pitches between solder balls and tighter dimensional controls possible.

Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash.

Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash.

Abstract: A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing. The second openings expose selective regions of a conductor layer. The multi-layer circuit board provides for less occurrences of delamination.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.

Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.

Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.

Abstract: A method and apparatus for improving the laminate performance of the solder balls in a BGA package. Specifically, the ball pads on the substrate are configured to increase the shear force necessary to cause delamination of the solder balls. Conductive traces extending planarly from the pads and arranged in specified configurations will increase the shear strength of the pad.

Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.

Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.

Abstract: A method for inhibiting damage caused to semiconductor die packages during a molding process, and the semiconductor die packages formed therefrom, is described. One or more openings are provided in a die carrier which are filled with a material which is more resistant to compressive forces than the carrier.

Abstract: An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

Abstract: A method for inhibiting damage caused to semiconductor die packages during a molding process, and the semiconductor die packages formed therefrom, is described. One or more openings are provided in a die carrier which are filled with a material which is more resistant to compressive forces than the carrier.

Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided. Preferably, the pin one indicator/alignment fiducial is placed adjacent a corner area of a ball grid array, and comprises an “L”-shaped narrow opening in a solder mask layer in which two lines, mutually perpendicular to one another, form components of an X-Y axis. The pin one indicator/alignment fiducial of the present invention is configured to provide only a minimal opening in the solder resist, making smaller pitches between solder balls and tighter dimensional controls possible.

Abstract: A method and device for providing a relief area on the surface of a molded I/C package. Specifically, a method of reducing delamination at the gate area of a molded I/C package by disposing an area of patterned metal traces on the substrate surface to form a relief area. The relief area will permit the I/C package to be broken away form the molding apparatus while reducing the possibility of delamination or Au/Cu burs at the gate area.

Abstract: A method and device for providing a relief area on the surface of a molded I/C package. Specifically, a method of reducing delamination at the gate area of a molded I/C package by disposing an area of patterned metal traces on the substrate surface to form a relief area. The relief area will permit the I/C package to be broken away form the molding apparatus while reducing the possibility of delamination or Au/Cu burs at the gate area.