Patents by Inventor Brandon C. MARIN

Brandon C. MARIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210125912
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 29, 2021
    Inventors: Zhiguo QIAN, Gang DUAN, Kemal AYGÜN, Jieying KONG, Brandon C. MARIN
  • Publication number: 20210091030
    Abstract: Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Inventors: Brandon C. Marin, Srinivas V. Pietambaram, Kristof Darmawikarta, Gang Duan, Sameer Paital
  • Publication number: 20210066447
    Abstract: Embodiments herein relate to a capacitor device or a manufacturing process flow for creating a capacitor that includes nanoislands within a package. The capacitor a first conductive plate having a first side and a second side opposite the first side and a second conductive plate having a first side and a second side opposite the first side where the first side of the first conductive plate faces the first side of the second conductive plate. A first plurality of nanoislands is distributed on the first side of the first conductive plate and a second plurality of nanoislands is distributed on the first side of the second conductive plate, where the first conductive plate, the second conductive plate, and the first and second pluralities of nanoislands form a capacitor. The nanoislands may be applied to the conductive plates using a sputtering technique.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 4, 2021
    Inventors: Srinivas PIETAMBARAM, Brandon C. MARIN, Jeremy ECTON, Hiroki TANAKA, Frank TRUONG
  • Patent number: 10923443
    Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D Ecton
  • Patent number: 10910327
    Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Brandon C Marin, Vahidreza Parichehreh, Jeremy D Ecton
  • Publication number: 20210028101
    Abstract: Embodiments disclosed herein include electronic packages and methods of making such packages. In an embodiment, a package substrate comprises a substrate comprising a first dielectric material, a first trace embedded in the substrate, and a patch in direct contact with the first trace. In an embodiment, the patch comprises a second dielectric material that is different than the first dielectric material.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Bai NIE, Haobo CHEN, Gang DUAN, Brandon C. MARIN, Srinivas PIETAMBARAM
  • Publication number: 20210014972
    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 14, 2021
    Inventors: Brandon C. MARIN, Tarek IBRAHIM, Srinivas PIETAMBARAM, Andrew J. BROWN, Gang DUAN, Jeremy ECTON, Sheng C. LI
  • Publication number: 20200411413
    Abstract: A substrate for an electronic device may include a first layer, and the first layer may include dielectric material. The first layer may include a first interconnect, and the first interconnect may have a first interconnect profile. The substrate may include a second layer, and the second layer may include dielectric material. The second layer may include a second interconnect, and the second interconnect may have a second interconnect profile. The first interconnect profile may be indicative of a subtractive manufacturing operation and the second interconnect profile may be indicative of an additive manufacturing operation.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Amruthavalli Pallavi Alur, Brandon C. Marin, Yikang Deng, Liwei Cheng, Jeremy D. Ecton, Andrew J. Brown, Lauren A. Link, Cheng Xu, Prithwish Chatterjee, Ying Wang
  • Publication number: 20200402720
    Abstract: A device is disclosed. The device includes a first insulating film structure, a plurality of conductor layers above the first insulating film structure, a Ti structure and a nanocube structure between respective layers of the plurality of conductor layers, the nanocube structure above the Ti structure, and a second insulating film structure above a topmost conductor layer of the plurality of conductor layers.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Brandon C. MARIN, Andrew J. BROWN, Kristof DARMAWIKARTA, Jeremy ECTON, Suddhasattwa NAD
  • Publication number: 20200395317
    Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes first waveguides over a package substrate. The first waveguides include first angled conductive layers, first transmission lines, and first cavities. The semiconductor package also includes a first dielectric over the first waveguides and package substrate, second waveguides over the first dielectric and first waveguides, and a second dielectric over the second waveguides and first dielectric. The second waveguides include second angled conductive layers, second transmission lines, and second cavities. The first angled conductive layers are positioned over the first transmission lines and package substrate having a first pattern of first triangular structures.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Brandon C. MARIN, Aleksandar ALEKSOV, Georgios DOGIAMIS, Jeremy D. ECTON, Suddhasattwa NAD, Mohammad Mamunur RAHMAN
  • Publication number: 20200373157
    Abstract: A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 ?m in thickness, and a second electrode is over the cured PID.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Inventors: Jeremy D. ECTON, Brandon C. MARIN, Andrew J. BROWN, Dilan SENEVIRATNE
  • Publication number: 20200373261
    Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Brandon C. MARIN, Jeremy D. ECTON, Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Yonggang LI, Dilan SENEVIRATNE
  • Publication number: 20200328131
    Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 15, 2020
    Inventors: Brandon C. MARIN, Kristof DARMAWIKARTA, Roy DITTLER, Jeremy ECTON, Darko GRUJICIC
  • Publication number: 20200312787
    Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Yonggang Li, Brandon C. Marin, Vahidreza Parichehreh, Jeremy D. Ecton
  • Publication number: 20200312793
    Abstract: A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Brandon C. Marin, Shivasubramanian Balasubramanian, Rahul Jain, Praneeth Akkinepally, Jeremy D. Ecton
  • Publication number: 20200258800
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 13, 2020
    Inventors: Jeremy ECTON, Oscar OJEDA, Leonel ARANA, Suddhasattwa NAD, Robert MAY, Hiroki TANAKA, Brandon C. MARIN
  • Publication number: 20200253037
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
  • Publication number: 20200144359
    Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.
    Type: Application
    Filed: January 8, 2020
    Publication date: May 7, 2020
    Inventors: Brandon C. Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong
  • Publication number: 20200083164
    Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Brandon C. MARIN, Frank TRUONG, Shivasubramanian BALASUBRAMANIAN, Dilan SENEVIRATNE, Yonggang LI, Sameer PAITAL, Darko GRUJICIC, Rengarajan SHANMUGAM, Melissa WETTE, Srinivas PIETAMBARAM
  • Patent number: 10546916
    Abstract: Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Brandon C Marin, Praneeth Akkinepally, Whitney Bryks, Dilan Seneviratne, Frank Truong