Patents by Inventor Brandon C. MARIN

Brandon C. MARIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230080454
    Abstract: An optoelectronic assembly is disclosed, comprising a substrate having a core comprised of glass, and a photonic integrated circuit (PIC) and an electronic IC (EIC) coupled to a first side of the substrate. The core comprises a waveguide with a first endpoint proximate to the first side and a second endpoint exposed on a second side of the substrate orthogonal to the first side. The first endpoint of the waveguide is on a third side of the core parallel to the first side of the substrate. The substrate further comprises an optical via aligned with the first endpoint, and the optical via extends between the first side and the third side. In various embodiments, the waveguide is of any shape that can be inscribed by a laser between the first endpoint and the second endpoint.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Applicant: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Brandon C. Marin, Debendra Mallik, Tarek A. Ibrahim, Jeremy Ecton, Omkar G. Karhade, Bharat Prasad Penmecha, Xiaoqian Li, Nitin A. Deshpande, Mitul Modi, Bai Nie
  • Publication number: 20230077486
    Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first via is through the core, where the first via comprise a conductive material, and a film over the first surface of the core, where the film is an adhesive. In an embodiment, a second via is through the film, where the second via comprises a conductive material, where the second via contacts the first via. In an embodiment, a centerline of the second via is aligned with a centerline of the first via. In an embodiment, a buildup layer is over the film.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Jeremy D. ECTON, Brandon C. MARIN, Aleksandar ALEKSOV, Srinivas V. PIETAMBARAM, Leonel ARANA
  • Publication number: 20230079607
    Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a first layer comprising glass. In an embodiment, conductive pillars are formed through the first layer, and a buildup layer stack is on the first layer. In an embodiment, conductive routing is provided through the buildup layer stack. In an embodiment, a second layer is over a surface of the buildup layer stack opposite from the glass layer.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Jeremy D. ECTON, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Suddhasattwa NAD, Leonel ARANA
  • Publication number: 20230078099
    Abstract: A substrate of a microelectronic assembly is provided, the substrate comprising conductive traces through an organic dielectric, and a coating comprising silicon and oxygen. The substrate is configured to couple with a component electrically and mechanically by at least one or more conductive via through the coating, the conductive via being electrically connected to the conductive traces, such that the coating is between the organic dielectric and the component when coupled. In some embodiments, the component includes another coating comprising silicon and oxygen, with conductive vias through the second coating. The conductive vias and the coating of the substrate are configured to bind with the conductive vias and the coating of the component respectively to form hybrid bonds.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Gang Duan, Srinivas V. Pietambaram, Brandon C. Marin, Bai Nie
  • Patent number: 11605867
    Abstract: A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Jeremy D. Ecton, Aleksandar Aleksov, Kristof Darmawikarta, Yonggang Li, Dilan Seneviratne
  • Publication number: 20230076917
    Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Inventors: Hiroki Tanaka, Brandon C. Marin, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Jeremy D. Ecton, Hari Mahalingam, Benjamin Duong
  • Publication number: 20230072096
    Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Inventors: Hiroki Tanaka, Brandon C. Marin, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Jeremy D. Ecton, Rajeev Ranjan
  • Publication number: 20230071707
    Abstract: An electro-optical system having one or more electro-optical devices integrally formed within a substrate and associated methods are disclosed. An electro-optical system including an electro-optic switch is shown. An electro-optical system including an electro-optic modulator is shown. An electro-optical system including an optical resonator is shown.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Inventors: Hiroki Tanaka, Brandon C. Marin, Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram
  • Publication number: 20230057384
    Abstract: Embodiments disclosed herein include carriers and methods of using the carriers to assemble electronic packages. In an embodiment, a carrier for electronic packaging assembly comprises a mold layer with a first surface and a second surface. In an embodiment, a plurality of glass substrates are embedded in the mold layer. In an embodiment, individual ones of the glass substrates comprise a third surface and a fourth surface, where the third surface of the glass substrate is substantially coplanar with the first surface of the mold layer.
    Type: Application
    Filed: August 20, 2021
    Publication date: February 23, 2023
    Inventors: Jeremy D. ECTON, Brandon C. MARIN, Hiroki TANAKA, Jason M. GAMBA, Srinivas V. PIETAMBARAM
  • Publication number: 20220406512
    Abstract: Techniques and mechanisms for providing structures of a magnetic material based inductor. In an embodiment, an inductor comprises a body of a magnetic material, and a conductor which extends along a surface of the body. The body comprises a carrier material and magnetic filler particles distributed in the carrier material. A passivation material of the inductor is provided adjacent to the conductor and to surfaces of the filler particles. The conductor and the passivation material comprise different respective material compositions, wherein the passivation material comprises one of nickel, tin, copper, palladium, or gold. In another embodiment, the inductor is one of a plated through hole inductor type of a planar inductor type.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 22, 2022
    Applicant: Intel Corporation
    Inventors: Xin Ning, Kyu-oh Lee, Brent Williams, Brandon C. Marin, Tarek A. Ibrahim, Krishna Bharath, Sai Vadlamani
  • Publication number: 20220406736
    Abstract: Disclosed herein are high-permeability magnetic thin films for coaxial metal inductor loop structures formed in through glass vias of a glass core package substrate, and related methods, devices, and systems. Exemplary coaxial metal inductor loop structures include a high-permeability magnetic layer within and on a surface of a through glass via extending through the glass core package substrate and a conductive layer on the high-permeability magnetic layer.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 22, 2022
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Srinivas Pietambaram, Suddhasattwa Nad, Jeremy Ecton
  • Publication number: 20220399278
    Abstract: An electronic substrate may be fabricated having a primary interposer comprising a laminate with a metal via through the laminate, two or more secondary interposers attached to a first side of the primary interposer, where respective sidewalls of the two or more secondary interposers define one or more recesses over the primary interposer, and an embedded component within a recess of the one or more recesses defined by the respective sidewalls of the two or more secondary interposers. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 15, 2022
    Applicant: Intel Corporation
    Inventor: Brandon C. Marin
  • Publication number: 20220399307
    Abstract: An electronic substrate may be fabricated having a core comprising a laminate including a metal layer between a first insulator layer and a second insulator layer, a metal via through the core, and metallization features on a first side and a second side of the core, wherein first ones of the metallization features are embedded within dielectric material on the first side of the core, and wherein a sidewall of the dielectric material and of the first insulator layer defines a recess over an area of the metal layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 10, 2021
    Publication date: December 15, 2022
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Sai Vadlamani, Omkar Karhade, Tolga Acikalin
  • Patent number: 11462432
    Abstract: A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Frank Truong, Praneeth Akkinepally, Chelsea M. Groves, Whitney M. Bryks, Jason M. Gamba, Brandon C. Marin
  • Publication number: 20220196914
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Jeremy D. ECTON, Hiroki TANAKA, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Gang DUAN, Bai NIE, Haobo CHEN, Zhichao ZHANG, Sai VADLAMANI, Aleksandar ALEKSOV
  • Publication number: 20220197044
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to a dual polarization chiplet that may be used by an optical receiver to split multi-polarized light traveling on a single fiber and carrying two or more light signals into two or more fibers each carrying the particular light signal. The dual polarization chiplet may also be used by an optical transmitter to combine multiple light signals to be transmitted onto a single fiber, where each of the multiple light signals are represented by a different polarization of a wavelength on the single fiber. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Kaveh HOSSEINI, Conor O'KEEFFE, Brandon C. MARIN, Hiroki TANAKA
  • Publication number: 20220187548
    Abstract: Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Inventors: Brandon C. MARIN, Divya PRATAP, Hiroki TANAKA, Nitin DESHPANDE, Omkar KARHADE, Robert Alan MAY, Sri Ranga Sai BOYAPATI, Srinivas V. PIETAMBARAM, Xiaoqian LI, Sai VADLAMANI, Jeremy ECTON
  • Publication number: 20220190918
    Abstract: Embodiments disclosed herein include photonics systems with a dual polarization module. In an embodiment, a photonics patch comprises a patch substrate, and a photonics die over a first surface of the patch substrate. In an embodiment, a multiplexer is over a second surface of the patch substrate. In an embodiment, a first optical path from the photonics die to the multiplexer is provided for propagating a first optical signal, and a second optical path from the photonics die to the multiplexer is provided for propagating a second optical signal. In an embodiment, a Faraday rotator is provided along the second optical path to convert the second optical signal from a first mode to a second mode before reaching the multiplexer.
    Type: Application
    Filed: December 11, 2020
    Publication date: June 16, 2022
    Inventors: Brandon C. MARIN, Kaveh HOSSEINI, Conor O'KEEFFE, Hiroki TANAKA
  • Publication number: 20220187549
    Abstract: Embodiments disclosed herein include photonics package with Faraday rotators to improve efficiency. In an embodiment, a photonics package comprises a package substrate and a compute die over the package substrate. In an embodiment, the photonics package further comprises a photonics die over the package substrate. In an embodiment, the compute die is communicatively coupled to the photonics die by a bridge in the package substrate. In an embodiment, the photonics package further comprises an integrated heat spreader (IHS) over the package substrate, and a Faraday rotator passing through the IHS and optically coupled to the photonics die.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Inventors: Hiroki TANAKA, Brandon C. MARIN, Kristof DARMAWKARTA, Robert Alan MAY, Sri Ranga Sai BOYAPATI, Srinivas V. PIETAMBARAM
  • Publication number: 20220165695
    Abstract: Embodiments disclosed herein include electronic packages with fin pitch first level interconnects. In an embodiment, the electronic package comprises a die and a package substrate attached to the die by a plurality of first level interconnects (FLIs). In an embodiment, individual ones of the plurality of FLIs comprise, a first pad on the package substrate, a solder on the first pad, a second pad on the die, and a bump on the second pad. In an embodiment, the bump comprises a porous nanostructure, and the solder at least partially fills the porous nanostructure.
    Type: Application
    Filed: November 25, 2020
    Publication date: May 26, 2022
    Inventors: Numair AHMED, Kyu-Oh LEE, Brandon C. MARIN, Gang DUAN