Patents by Inventor Bratin Saha

Bratin Saha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8140773
    Abstract: A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have any arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: March 20, 2012
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Gad Sheaffer, Quinn Jacobson
  • Publication number: 20120066457
    Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.
    Type: Application
    Filed: March 14, 2011
    Publication date: March 15, 2012
    Inventors: Benjamin C. Hertzberg, Bratin Saha, Ali-Reza Adl-Tabatabai
  • Patent number: 8132158
    Abstract: A method and apparatus for ensuring integrity of transaction exit functions is herein described. Dead local data in a transaction is prevented from overwriting local variables associated with a transaction exit function. In a write-buffering Software Transactional Memory (STM) system, a commit function is associated with a private stack to store local variables to ensure write-back of local dead data in a write-buffer does not corrupt the commit function. Similarly, in a roll-back STM, an abort function is associated with a private stack to store local variables to ensure the roll-back of a program stack with local dead data from a write log does not corrupt the abort function. Alternatively, one stack may be used for the transaction including a first function and an exit function. Here, local dead variables are detected and prevented from overwriting local variables of the exit function.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: March 6, 2012
    Inventors: Cheng Wang, Youfeng Wu, Bratin Saha, Ali-Reza Adl-Tabatabai
  • Patent number: 8108627
    Abstract: A transactional memory system, method and apparatus are disclosed. An embodiment of the method includes attempting to acquire a write lock provided by an implementation of a software transactional memory (STM) system for each of a set of memory locations of the STM; if a write lock is acquired for each of the set of memory locations, comparing the value in each of the set of memory locations to a corresponding expected value; and if the comparing yields the same, predetermined result for each of the set of memory locations, storing in each memory location a corresponding new value. Other embodiments are also described and claimed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: January 31, 2012
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai
  • Publication number: 20120023296
    Abstract: A page table entry dirty bit system may be utilized to record dirty information for a software distributed shared memory system. In some embodiments, this may improve performance without substantially increasing overhead because the dirty bit recording system is already available in certain processors. By providing extra bits, coherence can be obtained with respect to all the other uses of the existing page table entry dirty bits.
    Type: Application
    Filed: May 11, 2010
    Publication date: January 26, 2012
    Inventors: Shoumeng Yan, Ying Gao, Xiaocheng Zhou, Hu Chen, Sai Luo, Bratin Saha
  • Publication number: 20120016853
    Abstract: A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.
    Type: Application
    Filed: September 27, 2011
    Publication date: January 19, 2012
    Inventors: Cheng Wang, Youfeng Wu, Wei-Yu Chen, Bratin Saha, Ali Reza Adl-Tabatabai
  • Patent number: 8099538
    Abstract: In one embodiment, the present invention includes a method for accessing a shared memory associated with a reader-writer lock according to a first concurrency mode, dynamically changing from the first concurrency mode to a second concurrency mode, and accessing the shared memory according to the second concurrency mode. In this way, concurrency modes can be adaptively changed based on system conditions. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: January 17, 2012
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai
  • Patent number: 8095824
    Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: January 10, 2012
    Assignee: Intel Corporation
    Inventors: Jan Gray, Martin Taillefer, Yossi Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod Grover, Mike Magruder, Matt Tolton, Bratin Saha, Gad Sheaffer, Vadim Bassin
  • Publication number: 20110320776
    Abstract: A method and apparatus for designating and handling irrevocable transactions is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.
    Type: Application
    Filed: September 13, 2011
    Publication date: December 29, 2011
    Inventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
  • Patent number: 8086827
    Abstract: A method and apparatus for designating and handling irrevocable transaction is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designated as irrevocable. In response to designating a transaction as irrevocable, Single Owner Read Locks (SORLs) are acquired for previous and subsequent reads in the irrevocably designated transaction to ensure the transaction is able to complete without modification to locations read from, while permitting remote resources to load from those locations to continue execution.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: Adam Welc, Bratin Saha, Ali-Reza Adl-Tabatabai
  • Patent number: 8078807
    Abstract: A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value. In response to the private store, a cache line holding the value is transitioned to a private state, to ensure the value is not made globally visible. Upon eviction of the privately held cache line, the information is not written-back to ensure locality of the value. In one embodiment, the address based table includes a transactional write buffer to hold addresses, which correspond to tentatively updated values during a transaction. Accesses to the tentative values during the transaction may be accelerated through use of annotation bits and private stores as discussed herein. Upon commit of the transaction, the values are copied to the location to make the updates globally visible.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: December 13, 2011
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Ethan Schuchman
  • Patent number: 8065490
    Abstract: In accordance with some embodiments, software transactional memory may be used for both managed and unmanaged environments. If a cache line is resident in a cache and this is not the first time that the cache line has been read since the last write, then the data may be read directly from the cache line, improving performance. Otherwise, a normal read may be utilized to read the information. Similarly, write performance can be accelerated in some instances to improve performance.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Tatiana Shpeisman, Cheng Wang
  • Patent number: 8065491
    Abstract: A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.
    Type: Grant
    Filed: December 30, 2007
    Date of Patent: November 22, 2011
    Assignee: Intel Corporation
    Inventors: Tatiana Shpeisman, Ali-Reza Adl-Tabatabai, Vijay Menon, Bratin Saha
  • Patent number: 8060482
    Abstract: A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 15, 2011
    Assignee: Intel Corporation
    Inventors: Cheng Wang, Youfeng Wu, Wei-Yu Chen, Bratin Saha, Ali-Reza Adl-Tabatabai
  • Publication number: 20110276761
    Abstract: A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value. In response to the private store, a cache line holding the value is transitioned to a private state, to ensure the value is not made globally visible. Upon eviction of the privately held cache line, the information is not written-back to ensure locality of the value. In one embodiment, the address based table includes a transactional write buffer to hold addresses, which correspond to tentatively updated values during a transaction. Accesses to the tentative values during the transaction may be accelerated through use of annotation bits and private stores as discussed herein. Upon commit of the transaction, the values are copied to the location to make the updates globally visible.
    Type: Application
    Filed: May 10, 2011
    Publication date: November 10, 2011
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Etban Schuchman
  • Publication number: 20110271017
    Abstract: A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.
    Type: Application
    Filed: July 13, 2011
    Publication date: November 3, 2011
    Inventors: Tatiana Shpeisman, Ali-Reza Adl-Tabatabai, Vijay Menon, Bratin Saha
  • Publication number: 20110197029
    Abstract: A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.
    Type: Application
    Filed: April 26, 2011
    Publication date: August 11, 2011
    Inventors: Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn Jacobson
  • Patent number: 7991965
    Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Quinn A. Jacobson, Anne Weinberger Bracy, Hong Wang, John P. Shen, Per Hammarlund, Matthew C. Merten, Suresh Srinivas, Kshitij A. Doshi, Gautham N. Chinya, Bratin Saha, Ali-Reza Adl-Tabatabai, Gad S. Sheaffer
  • Publication number: 20110153957
    Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit) GPU and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Inventors: Ying Gao, Hu Chen, Shoumeng Yan, Xiaocheng Zhou, Sai Luo, Bratin Saha
  • Publication number: 20110145512
    Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Inventors: Ali-Reza Adl-Tabatabai, Yang Ni, Bratin Saha, Vadim Bassin, Gad Sheaffer, David Callahan, Jan Gray