Abstract: A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions.

Abstract: A method to perform validation of a read set of a transaction is presented. In one embodiment, the method compares a read signature of a transaction to a plurality of write signatures associated with a plurality of transactions. The method determines based on the result of comparison, whether to update a local value of the transaction to a commit value of another transaction from the plurality of the transactions.

Abstract: A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring ownership of meta-data associated with a data element, the meta-data is updated with an ownership reference to a transaction to enable efficient subsequent ownership tests. However, during validation, for some conditions, meta-data is updated from the ownership reference to a write entry reference to enable efficient validation.

Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.

Abstract: According to one embodiment of the invention, a method comprises verifying that a cache block is not exclusively owned, and if not, transmitting a message identifying both the cache block and a caching agent requesting ownership of the cache block to a broadcast interconnect.

Abstract: A method and apparatus for accelerating lookups in an address based table is herein described. When an address and value pair is added to an address based table, the value is privately stored in the address to allow for quick and efficient local access to the value. In response to the private store, a cache line holding the value is transitioned to a private state, to ensure the value is not made globally visible. Upon eviction of the privately held cache line, the information is not written-back to ensure locality of the value. In one embodiment, the address based table includes a transactional write buffer to hold addresses, which correspond to tentatively updated values during a transaction. Accesses to the tentative values during the transaction may be accelerated through use of annotation bits and private stores as discussed herein. Upon commit of the transaction, the values are copied to the location to make the updates globally visible.

Abstract: A method and apparatus for providing optimized strong atomicity operations for non-transactional writes is herein described. Locks are acquired upon initial non-transactional writes to memory locations. The locks are maintained until an event is detected resulting in the release of the locks. As a result, in the intermediary period between acquiring and releasing the locks, any subsequent writes to memory locations that are locked are accelerated through non-execution of lock acquire operations.

Abstract: A method and apparatus for providing efficient strong atomicity is herein described. Optimized strong operations may be inserted at non-transactional read accesses to provide efficient strong atomicity. A global transaction value is copied at a beginning of a non-transational function to a local transaction value; essentially creating a local timestamp of the global transaction value. At a non-transactional memory access within the function, a counter value or version value is compared to the LTV to see if a transaction has started updating memory locations, or specifically the memory location accessed. If memory locations have not been updated by a transaction, execution is accelerated by avoiding a full set of slowpath strong atomic operations to ensure validity of data accessed. In contrast, the slowpath operations may be executed to resolve contention between a transactional and non-transaction access contending for the same memory location.

Abstract: Embodiments of a system and method for transactional memory (TM) with automatic object versioning are described. Embodiments described herein include a TM system and method that facilitates the execution of object-oriented application programs in a transactional environment, including automatically versioning objects to enhance efficiency. Embodiments of the TM automatically designate versions of objects using pointers, accurately identifying usable and unusable versions. Object versioning as described herein allows the garbage collector to easily and efficiently determine which objects may be moved, freeing memory space and reducing the number of objects traversed by a transaction before finding a useable version of an object. Other embodiments are described and claimed.

Abstract: A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to facilitate synchronization between parallel processes. According to an aspect, an instruction set architecture includes circuitry that handles a speculative execution instruction and a speculation termination instruction. The speculative execution instruction may be an instruction that takes first and second operands, causes the processor to speculatively execute additional instructions if a memory location contains a value, and causes the processor to start executing instructions from an address indicated by the second operand if a mis-speculation occurs, and the speculation termination instruction may be an instruction that causes the processor to begin retiring the additional instructions.

Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract: In accordance with some embodiments, software transactional memory may be used for both managed and unmanaged environments. If a cache line is resident in a cache and this is not the first time that the cache line has been read since the last write, then the data may be read directly from the cache line, improving performance. Otherwise, a normal read may be utilized to read the information. Similarly, write performance can be accelerated in some instances to improve performance.

Abstract: Object-based conflict detection is described in the context of software transactional memory. In one example, a pointer is received for a block of instructions, the block of instructions having allocated objects. The lower bits of the pointer are masked if the pointer is in a small object space to obtain a block header for the block, and a size of the allocated objects is determined using the block header.

Abstract: Object-based conflict detection is described in the context of software transactional memory. In one example, a block of instructions is received for execution as an object in a software transactional memory transaction. The base of the object is computed, a lock is found for the object using the base of the object.

Abstract: A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to facilitate synchronization between parallel processes. According to an aspect, an instruction set architecture includes circuitry that handles a speculative execution instruction and a speculation termination instruction. The speculative execution instruction may be an instruction that takes first and second operands, causes the processor to speculatively execute additional instructions if a memory location contains a value, and causes the processor to start executing instructions from an address indicated by the second operand if a mis-speculation occurs, and the speculation termination instruction may be an instruction that causes the processor to begin retiring the additional instructions.

Abstract: Memory reclamation with optimistic concurrency is described. In one example an allocated memory object is tentatively freed in a software transactional memory, the object having pointers into it from at least one transaction. A time when all transactions that are outstanding at the time an object is tentatively freed have ended is detected, and the object is actually freed based on the detection.

Abstract: A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have any arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred.

Abstract: A method and apparatus for accelerating a software transactional memory (STM) system is described herein. Annotation field are associated with lines of a transactional memory. An annotation field associated with a line of the transaction memory is initialized to a first value upon starting a transaction. In response to encountering a read operation in the transaction, then annotation field is checked. If the annotation field includes a first value, the read is serviced from the line of the transaction memory without having to search an additional write space. A second and third value in the annotation field potentially indicates whether a read operation missed the transactional memory or a tentative value is stored in a write space. Additionally, an additional bit in the annotation field, may be utilized to indicate whether previous read operations have been logged, allowing for subsequent redundant read logging to be reduced.

Abstract: A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries.