Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks.

Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.

Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

Abstract: A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which models the delay in transmission of the internal Write Valid signal and system clock distribution to the deserializers in the data path portion of the write path, which is otherwise controlled by the intermittently asserted write strobe signal. With the input distribution delay of the system clock (Clk) and the write strobe (WS) matched by design, the distributed system clock and Write Valid signal are synchronized to the WS distribution path by means of the DLL delay with reference to the system clock input to the DLL.

Abstract: A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and delaying the input of the start signal to a second counter upstream of the locked loop to delay the initiation of a running count of control clock pulses by an amount equal to a predetermined delay. Another disclosed method is for controlling the output of data from a memory device comprising deriving from an external clock signal a control clock for operating an array of storage cells and a read clock, both the control clock and the read clock being comprised of clock pulses. A start signal is generated for initiating production of a running count of the read clock pulses in a first counter. The start signal may be produced when a locked loop achieves a lock between the read clock and the control clock.

Abstract: A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAMs are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

Abstract: An apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.

Abstract: An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.