Patents by Inventor Brent Keeth

Brent Keeth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • OPTICAL INTERCONNECT IN HIGH-SPEED MEMORY SYSTEMS
    Publication number: 20140281199
    Abstract: A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.
    Type: Application
    Filed: April 28, 2014
    Publication date: September 18, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jacob Baker, Brent Keeth
  • APPARATUSES AND METHODS FOR MEMORY TESTING AND REPAIR
    Publication number: 20140281693
    Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Joe M. Jeddeloh, Brent Keeth
  • FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY
    Publication number: 20140281204
    Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.
    Type: Application
    Filed: June 17, 2013
    Publication date: September 18, 2014
    Inventors: Joe M. Jeddeloh, Brent Keeth
  • APPARATUS AND METHODS FOR FORMING A MEMORY CELL USING CHARGE MONITORING
    Publication number: 20140233298
    Abstract: Apparatuses and methods of forming a memory cell is described. In one such method, a forming charge applied to a memory cell, such as a Resistive RAM (RRAM) memory cell, is monitored to determine the progress of the forming the cell. If the cell is consuming charge too slowly, a higher voltage can be applied. If the cell is consuming charge too quickly, a lower voltage can be applied. The charge may be monitored by charging a capacitor to a certain level, then monitoring the discharge rate of the capacitor though the cell. The monitoring may use comparators to measure the charge. The monitoring may also use an analog to digital converter to perform the monitoring.
    Type: Application
    Filed: February 20, 2013
    Publication date: August 21, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Brent Keeth, Durai Vishak Nirmal Ramaswamy, Gurtej S. Sandhu, Adam D. Johnson, Scott E. Sills, Alessandro Calderoni
  • Stacked device remapping and repair
    Patent number: 8787101
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • RESISTIVE MEMORY SENSING
    Publication number: 20140169066
    Abstract: The present disclosure includes apparatuses and methods for sensing a resistive memory cell. A number of embodiments include performing a sensing operation on a memory cell to determine a current value associated with the memory cell, applying a programming signal to the memory cell, and determining a data state of the memory cell based on the current value associated with the memory cell before applying the programming signal and a current value associated with the memory cell after applying the programming signal.
    Type: Application
    Filed: June 19, 2013
    Publication date: June 19, 2014
    Applicant: Micro Technology, Inc.
    Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu, Lei Bi, Adam D. Johnson, Brent Keeth, Alessandro Calderoni, Scott E. Sills
  • Optical interconnect in high-speed memory systems
    Patent number: 8712249
    Abstract: A optical link for achieving electrical isolation between a controller and a memory device is disclosed. The optical link increases the noise immunity of electrical interconnections, and allows the memory device to be placed a greater distance from the processor than is conventional without power-consuming I/O buffers.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Russel J. Baker, Brent Keeth
  • STACKED DEVICE REMAPPING AND REPAIR
    Publication number: 20130329510
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Application
    Filed: August 5, 2013
    Publication date: December 12, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Stacked device remapping and repair
    Patent number: 8503258
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 6, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH MULTIPLE THERMAL PATHS AND ASSOCIATED SYSTEMS AND METHODS
    Publication number: 20130119528
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Application
    Filed: September 13, 2012
    Publication date: May 16, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet Gandhi
  • SIGNAL DELIVERY IN STACKED DEVICE
    Publication number: 20130036606
    Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.
    Type: Application
    Filed: January 30, 2012
    Publication date: February 14, 2013
    Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
  • STACKED DEVICE REMAPPING AND REPAIR
    Publication number: 20130003473
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 3, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • Stacked device remapping and repair
    Patent number: 8320206
    Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: November 27, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
  • High density integrated circuitry for semiconductor memory having memory cells with a minimum capable photolithographic feature dimension
    Patent number: 8299514
    Abstract: Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. A semiconductor memory device includes i) a total of no more than 68,000,000 functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells. At least one of the memory arrays contains at least 100-square microns of continuous die surface area having at least 128 of the functional and operably addressable memory cells. More preferably, at least 100 square microns of continuous die surface area have at least 170 of the functional and operably addressable memory cells.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: October 30, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Brent Keeth, Pierre Fazan
  • SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE
    Publication number: 20120246434
    Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
    Type: Application
    Filed: June 5, 2012
    Publication date: September 27, 2012
    Inventors: Jeffrey W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum
  • STACKED DEVICE IDENTIFICATION ASSIGNMENT
    Publication number: 20120161814
    Abstract: Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die.
    Type: Application
    Filed: March 5, 2012
    Publication date: June 28, 2012
    Inventor: Brent Keeth
  • System and method for decoding commands based on command signals and operating state
    Patent number: 8205055
    Abstract: A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: June 19, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jeffery W. Janzen, Brent Keeth, Jeffrey P. Wright, James S. Cullum
  • RECONFIGURABLE CONNECTIONS FOR STACKED SEMICONDUCTOR DEVICES
    Publication number: 20120133387
    Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.
    Type: Application
    Filed: February 6, 2012
    Publication date: May 31, 2012
    Inventor: Brent Keeth
  • 256 Meg dynamic random access memory
    Patent number: 8189423
    Abstract: A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: May 29, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Brent Keeth, Layne G. Bunker, Raymond J. Beffa, Frank F. Ross
  • Devices and methods for driving a signal off an integrated circuit
    Patent number: 8183880
    Abstract: Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: May 22, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Timothy Hollis, Brent Keeth