Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry which includes first single crystal transistors; a first metal layer atop first single crystal layer; a second, third, and fourth metal layer providing connections between the first transistors; at least one second level (includes a plurality of second transistors including metal gates, and a plurality of memory cells) atop the first level; a fourth metal layer above the second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid; a local power distribution grid, where the first level includes first Electrostatic Discharge (ESD) circuits, and the second level includes second ESD circuits.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.

Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits with a sense amplifier; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second transistors with a metal gate, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed atop the control circuits, which control data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, the average thickness of fourth metal-layer is at least twice the average thickness of second metal-layer; the fourth metal-layer includes a global power distribution grid.

Abstract: 3D semiconductor device including: a first level including first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the first single-crystal transistors; a first metal layer disposed atop the first single-crystal transistors; a second metal layer disposed atop the first metal layer, a second level disposed atop the second metal layer includes second transistors and a memory array of first memory cells, a third level including second memory cells which include some third transistors, which themselves include a metal gate and is disposed above the second level; a third metal layer disposed above the third level; a fourth metal layer disposed above the third metal layer, a connective path from the third metal layer to the second metal layer with a thru second level via of a diameter less than 800 nm which also passes thru the memory array, different write voltages for different dies.

Abstract: A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors, at least one metal layer, and third memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors, another at least one metal layer, and is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes; and a via connection through the second level and the third level, and where the fourth level includes at least one SRAM memory array.

Abstract: A semiconductor device including: a first level including a first single crystal silicon layer, a plurality of first transistors, and input/output circuits; a first metal layer; a second metal layer which includes a power delivery network; where interconnection of the plurality of first transistors includes the first and second metal layers; a second level including a plurality of metal gate second transistors and first array of memory cells, disposed over the first level; a third level including a plurality of metal gate third transistors and a second array of memory cells, disposed over the second level; a via disposed through the second and third levels; a third metal layer disposed over the third level; a fourth metal layer disposed over the third metal layer; and a fourth level disposed over the fourth metal layer and including a second single crystal silicon layer.

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors, including metal gate) atop the third metal layer; a fourth metal layer above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid including the fifth metal layer; a local power distribution grid, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer, a layer deposited by ALD.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

Abstract: A 3D semiconductor device including: a first level with first-transistors, a single crystal layer overlaid by at least one first metal-layer which includes interconnects between the first-transistors forming first control circuits with a sense amplifiers; the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second-transistors with a metal gate, overlaid by a third level which includes second memory cells which include third-transistors and are partially disposed atop the control circuits, which control the data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third-transistor gate locations are aligned to second-transistor gate locations within greater than 0.2 nm error, the average thickness of second metal-layer is at least twice the average thickness of the third metal-layer; the second metal-layer includes a global power distribution grid.

Abstract: A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.

Abstract: A 3D semiconductor device including dicing including an etch process; and including: a first level including a single crystal layer, and a memory control circuit which includes first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.

Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors which each includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

Abstract: A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a first oxide layer disposed atop of the first level; a second level including second transistors and at least one array of memory cells, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where the at least one of the second transistors includes a recessed channel, and where the second level is directly bonded to the first level.

Abstract: An interconnection structure, including: a first BEOL (Back-End-Of-Line) level which includes a first MLG (Multi-Layer Graphene) layer which includes at least one first line structure of MLG material; and a first isolation layer which includes an electrically isolating material and is disposed above and beside the at least one first line structure of MLG material; a second BEOL level which includes a second MLG layer (includes MLG material) disposed above the first isolation layer; a connection path electrically connecting first MLG layer to second MLG layer; and at least one via with serrated edges mitigating misalignment impacts and providing low via to line contact resistance, where the connection path includes one of the at least one via, where a width of the at least one first line structure of MLG material is greater than a diameter of the one of the at least one via, and where both MLG layers are intercalation doped.

Abstract: A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

Abstract: A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.

Abstract: A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.

Abstract: An integrated semiconductor device including: a first level; a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits each include first transistors, where the second level is disposed above the first level and includes a plurality of arrays of first memory cells, where the second level includes second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; and a third level, where the third level includes third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate area greater than 1,000 mm2.