Patents by Inventor Brian Cronquist

Brian Cronquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100646
    Abstract: A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; a via disposed through the second level; the device includes at least one temperature sensor; the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.
    Type: Grant
    Filed: April 1, 2024
    Date of Patent: September 24, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240315059
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; and a second level including a plurality of second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of memory cells, where each of the plurality of memory cells includes at least one of the second transistors, where the device includes at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 19, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 12094829
    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the second level includes at least one voltage regulator.
    Type: Grant
    Filed: July 25, 2021
    Date of Patent: September 17, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240304617
    Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 650 nm.
    Type: Application
    Filed: May 19, 2024
    Publication date: September 12, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240297169
    Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20240295691
    Abstract: A multi-level semiconductor device, the device comprising: a first level comprising integrated circuits; a second level comprising at least one electromagnetic wave receiver, wherein said second level is disposed above said first level, wherein said integrated circuits comprise single crystal transistors; and an oxide layer disposed between said first level and said second level, wherein said device comprises at least one read out circuit, wherein said second level is bonded to said oxide layer, and wherein said bonded comprises oxide to oxide bonds.
    Type: Application
    Filed: March 30, 2024
    Publication date: September 5, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 12080743
    Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of memory circuits.
    Type: Grant
    Filed: February 4, 2024
    Date of Patent: September 3, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 12080630
    Abstract: A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level overlays the first level and includes at least one single crystal silicon layer, where the second level includes a plurality of transistors and a plurality of second metal layers, each transistor of the plurality of transistors includes a single crystal channel, where the plurality of second metal layers include interconnections between transistors of the plurality of transistors, where the second level is overlaid by a first isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, where each of at least one of the plurality of transistors includes a two sided gate, and where the single crystal silicon layer thickness is less than two microns.
    Type: Grant
    Filed: December 8, 2023
    Date of Patent: September 3, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 12071121
    Abstract: An electrical passenger car, the electrical passenger car including: at least two electrically driven motors; a battery pack; motor control electronics; a communication control unit; where the motor control electronics are connected to the at least two electrically driven motors; wheels, where the wheels are connected to the at least two electrically driven motors; and sensors, where the sensors are connected to at least the motor control electronics, where the wheels include a first wheel and a second wheel, where the second wheel has a radius at least 7% greater than a radius of the first wheel, where the communication control unit is designed to communicate the motor control electronics with a cloud AI server, and where the electrical passenger car is designed to be driven on a paved road.
    Type: Grant
    Filed: April 8, 2024
    Date of Patent: August 27, 2024
    Assignee: Or-Ment LLC
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12068187
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
    Type: Grant
    Filed: January 27, 2024
    Date of Patent: August 20, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20240274523
    Abstract: A semiconductor device including: a first silicon layer including a first single crystal silicon layer; first transistors with a single crystal channel and overlaid by a first metal layer; overlaid by a second metal layer; overlaid by a third metal layer; a second level with second transistors and including a metal gate, and then disposed over the third metal layer; the second level is overlaid by a third level with third transistors; and then overlaid by a fourth metal layer; fourth overlaid by a fifth metal layer; a via disposed through the second level; the device includes at least one temperature sensor; the fifth metal layer average thickness is greater than the third metal layer average thickness by at least 50%; at least one element within at least one of the second transistors has been processed independently of the third transistors.
    Type: Application
    Filed: April 1, 2024
    Publication date: August 15, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240253611
    Abstract: An electrical passenger car, the electrical passenger car including: at least two electrically driven motors; a battery pack; motor control electronics; a communication control unit; where the motor control electronics are connected to the at least two electrically driven motors; wheels, where the wheels are connected to the at least two electrically driven motors; and sensors, where the sensors are connected to at least the motor control electronics, where the wheels include a first wheel and a second wheel, where the second wheel has a radius at least 7% greater than a radius of the first wheel, where the communication control unit is designed to communicate the motor control electronics with a cloud AI server, and where the electrical passenger car is designed to be driven on a paved road.
    Type: Application
    Filed: April 8, 2024
    Publication date: August 1, 2024
    Applicant: Or-Ment LLC
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12051674
    Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.
    Type: Grant
    Filed: March 14, 2024
    Date of Patent: July 30, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12041791
    Abstract: A semiconductor device including: a first level including a plurality of first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes a plurality of second memory arrays; and a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes (FFHs), where the second level includes second filled holes (SFHs), where the SFHs are aligned to the FFHs with a more than 1 nm but less than 40 nm alignment error, where the third level includes a plurality of Look-Up-Table circuits.
    Type: Grant
    Filed: February 2, 2024
    Date of Patent: July 16, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Patent number: 12033884
    Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one (ALO) second level on top of or above the second metal layer; performing a lithography step on the second level; forming ALO third level on top of or above the ALO second level; performing processing steps to form first memory cells within the ALO second level and second memory cells within the ALO third level, first memory cells include ALO second transistor, second memory cells include ALO third transistor, first metal layer thickness is at least 50% greater than the second metal layer thickness, ALO first transistor controls power delivery to ALO second transistor; then dicing using a laser system.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: July 9, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20240222368
    Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.
    Type: Application
    Filed: March 13, 2024
    Publication date: July 4, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240222333
    Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory cells which include second transistors, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed over the control circuits, which control data written to second memory cells; and a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, and the average thickness of fourth metal layer is at least twice the average thickness of second metal layer; the fourth metal layer includes a global power distribution grid.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12027518
    Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and first transistors; a first metal layer disposed over it; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including second transistors, disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 240 nm alignment error; where the fifth metal layer includes global power delivery; each of the third transistors comprises a metal gate; a via disposed through the second level and the third level, where a typical thickness of the second metal layer is greater than a typical thickness of the third metal layer by at least 50%.
    Type: Grant
    Filed: March 13, 2024
    Date of Patent: July 2, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12029050
    Abstract: A 3D semiconductor device including: a first level including a single crystal layer, and a memory control circuit which includes at least one temperature sensor circuit and first transistors; a first metal layer overlaying the first single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors—which may include a metal gate—disposed atop the third metal layer; third transistors disposed atop the second transistors; a fourth metal layer disposed atop the third transistors; a memory array including word-lines and at least four memory mini arrays (each mini array includes at least four rows by four columns of memory cells), each memory cell includes at least one second transistor or at least one third transistor; and a connection path from fourth metal to third metal, the path includes a via disposed through the memory array.
    Type: Grant
    Filed: December 19, 2023
    Date of Patent: July 2, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist, Eli Lusky
  • Publication number: 20240213073
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layer; a second metal layer overlaying the first metal layer; and a second level including a second single crystal layer, the second level including second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of DRAM memory cells, where each of the plurality of DRAM memory cells includes at least one of the second transistors and one capacitor, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
    Type: Application
    Filed: January 27, 2024
    Publication date: June 27, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar