Patents by Inventor Brian Cronquist

Brian Cronquist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12183699
    Abstract: A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: December 31, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20240429086
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a first oxide layer disposed atop of the first level; a second level including second transistors and at least one array of memory cells, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where the at least one of the second transistors includes a recessed channel, and where the second level is directly bonded to the first level.
    Type: Application
    Filed: September 9, 2024
    Publication date: December 26, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 12170248
    Abstract: An interconnection structure, including: a first BEOL (Back-End-Of-Line) level which includes a first MLG (Multi-Layer Graphene) layer which includes at least one first line structure of MLG material; and a first isolation layer which includes an electrically isolating material and is disposed above and beside the at least one first line structure of MLG material; a second BEOL level which includes a second MLG layer (includes MLG material) disposed above the first isolation layer; a connection path electrically connecting first MLG layer to second MLG layer; and at least one via with serrated edges mitigating misalignment impacts and providing low via to line contact resistance, where the connection path includes one of the at least one via, where a width of the at least one first line structure of MLG material is greater than a diameter of the one of the at least one via, and where both MLG layers are intercalation doped.
    Type: Grant
    Filed: March 15, 2024
    Date of Patent: December 17, 2024
    Assignee: DESTINATION 2D
    Inventors: Klaus Schuegraf, Kaustav Banerjee, Brian Cronquist
  • Publication number: 20240404866
    Abstract: A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 5, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20240395592
    Abstract: A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.
    Type: Application
    Filed: September 9, 2022
    Publication date: November 28, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 12154817
    Abstract: A method for producing a 3D memory device including: providing a first level including a first single-crystal layer and control circuits, where the first level includes at least two interconnecting metal layers; forming at least one second level disposed above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level; each of first memory cells include one first transistor and each of second memory cells include one second transistor, where first memory cells and second memory cells are a NAND nonvolatile type memory, and at least one of the second transistors include a metal gate.
    Type: Grant
    Filed: September 9, 2022
    Date of Patent: November 26, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20240389366
    Abstract: An integrated semiconductor device including: a first level; a second level, where the first level includes single crystal silicon and a plurality of logic circuits, where the plurality of logic circuits each include first transistors, where the second level is disposed above the first level and includes a plurality of arrays of first memory cells, where the second level includes second transistors, where each of the first memory cells includes at least one of the second transistors, where the first level is bonded to the second level; an array of processors; and a third level, where the third level includes third transistors, where the third level is disposed above the second level and includes a plurality of arrays of second memory cells, where each of the second memory cells includes at least one of the third transistors, where the device includes a substrate area greater than 1,000 mm2.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20240379553
    Abstract: A semiconductor device including: a first level including: a first silicon layer including a first single crystal silicon layer; first transistors each including a single-crystal channel; a first metal layer connected to the first transistors and the second metal layer; a third metal layer connected to the second metal layer; a second level including second transistors; a third level including third transistors, the third level is disposed over the second level which is disposed over the first level; a fifth metal layer disposed over a fourth metal layer disposed over the third level; and a via disposed through the second level, where at least one of the second transistors includes a metal gate, where the device includes at least one temperature sensor, and where at least one element within at least one of the second transistors has been processed independently of the third transistors.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240379502
    Abstract: A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.
    Type: Application
    Filed: July 20, 2024
    Publication date: November 14, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20240379624
    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a plurality of second transistors, where the second level includes a third layer, the third layer including first conductive lines; a third level overlaying the second level, where the third level includes a plurality of third transistors, where the third level includes a fourth layer, the fourth layer including second conductive lines; and a plurality of connection paths, where the plurality of connection paths provides electrical connections at least from a plurality of the first transistors to the plurality of third transistors, and where the first level includes at least one voltage regulator.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 14, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12144190
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; and a second level including a plurality of second transistors and at least one third metal layer, where the second level overlays the first level, where at least one of the second transistors includes a transistor channel, where the second level includes a plurality of memory cells, where each of the plurality of memory cells includes at least one of the second transistors, where the device includes at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit, where the second level is directly bonded to the first level, and where the bonded includes metal to metal bonds.
    Type: Grant
    Filed: May 29, 2024
    Date of Patent: November 12, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20240371906
    Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlying oxide disposed on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of image sensors, where the second level is bonded to the first level including an oxide to oxide bond; a plurality of pixel control circuits; a third level disposed underneath the first level, where the third level includes a plurality of third transistors, where the plurality of third transistors each include a single crystal channel; and a plurality of recessed channel transistors.
    Type: Application
    Filed: July 20, 2024
    Publication date: November 7, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 12136562
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; a first oxide layer disposed over the second metal layer; a second oxide layer disposed over the first oxide layer; and a second level including at least one array of memory cells and second transistors, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where at least one of the second transistors includes at least two independent gates, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.
    Type: Grant
    Filed: December 2, 2023
    Date of Patent: November 5, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20240363385
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
    Type: Application
    Filed: June 6, 2024
    Publication date: October 31, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Patent number: 12125737
    Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
    Type: Grant
    Filed: June 6, 2024
    Date of Patent: October 22, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar
  • Publication number: 20240339407
    Abstract: An interconnection structure, including: a first BEOL (Back-End-Of-Line) level which includes a first MLG (Multi-Layer Graphene) layer which includes at least one first line structure of MLG material; and a first isolation layer which includes an electrically isolating material and is disposed above and beside the at least one first line structure of MLG material; a second BEOL level which includes a second MLG layer (includes MLG material) disposed above the first isolation layer; a connection path electrically connecting first MLG layer to second MLG layer; and at least one via with serrated edges mitigating misalignment impacts and providing low via to line contact resistance, where the connection path includes one of the at least one via, where a width of the at least one first line structure of MLG material is greater than a diameter of the one of the at least one via, and where both MLG layers are intercalation doped.
    Type: Application
    Filed: March 15, 2024
    Publication date: October 10, 2024
    Inventors: Klaus SCHUEGRAF, Kaustav BANERJEE, Brian CRONQUIST
  • Publication number: 20240324166
    Abstract: A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes at least one SRAM memory array.
    Type: Application
    Filed: June 2, 2024
    Publication date: September 26, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Brian Cronquist
  • Publication number: 20240321832
    Abstract: A 3D semiconductor device including: a first level with first transistors, single crystal layer overlaid by at least one first metal layer which includes interconnects between the first transistors forming first control circuits with a sense amplifier, the first metal-layer(s) overlaid by a second metal-layer which is overlaid by a second level which includes first memory cells which include second transistors with a metal gate, overlaid by a third level which includes second memory cells which include third transistors and are partially disposed atop the control circuits, which control data written to second memory cells; a fourth metal-layer overlaying a third metal-layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within less than 100 nm, the average thickness of fourth metal-layer is at least twice the average thickness of second metal-layer; the fourth metal-layer includes a global power distribution grid.
    Type: Application
    Filed: May 19, 2024
    Publication date: September 26, 2024
    Applicant: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Publication number: 20240317206
    Abstract: An electrical passenger car, the electrical passenger car including: a battery pack; motor control electronics; a communication control unit; at least one electrically driven motor; wheels, where the wheels are connected to the at least one electrically driven motor; and sensors, where the sensors are connected to at least the motor control electronics, where the wheels include a first wheel and a second wheel, where the second wheel has a radius at least 7% greater than a radius of the first wheel, where the battery pack is mounted in a car frame such that the battery pack could be moved forward or backward, where the communication control unit is designed to communicate the motor control electronics with a cloud AI server, and where the electrical passenger car is designed to be driven on a paved road.
    Type: Application
    Filed: June 4, 2024
    Publication date: September 26, 2024
    Applicant: Or-Ment LLC
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 12100611
    Abstract: A method for producing 3D semiconductor devices including: providing a first level including first transistors and a first single crystal layer; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming at least one second level on top of or above the second metal layer; performing a lithography step on the second level; forming at least one third level on top of or above the second level; performing processing steps to form first memory cells within the second level and second memory cells within the third level, where the first memory cells include at least one second transistor, the second memory cells include at least one third transistor, second transistors comprise gate electrodes comprising metal, and then forming at least four independent memory arrays which include some first memory cells and/or second memory cells.
    Type: Grant
    Filed: November 14, 2023
    Date of Patent: September 24, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Deepak C. Sekar